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Inventor

Peter Ramyalal Suaris

Inventor
Camas, WA, US

Overview

7→
Patents
2001–2018
Patent span
Physics
Primary field (CPC G)

Patents· 7 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing47%
G11CStatic stores13%
H03KPulse technique13%
H10BElectronic memory devices13%
H10DInorganic electric semiconductor devices13%
PatentTitleYear
10,042,966Computing resource allocation based on flow graph translation2018RE045110'MPGA products based on a prototype FPGA'20147,716,622'Memory re-implementation for field programmable gate arrays'20107,673,273'MPGA products based on a prototype FPGA'20107,251,803'Memory re-implementation for field programmable gate arrays'20077,203,919'Retiming circuits using a cut-based approach'20076,223,334'Automatic topology synthesis and optimization'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2010Based in Camas, WA, US· patent location history
2007–2014Patents assigned to SUARIS PETER RAMYALAL (3)· patent assignee history
2007–2010Patents assigned to CHOU NAN-CHI (2)· patent assignee history
2007–2010Patents assigned to DING YUZHENG (2)· patent assignee history
2007–2010Patents assigned to LIU LUNG-TIEN (2)· patent assignee history
2010–2014Based in Danville, CA, US· patent location history
2014Patents assigned to MADURAWE RAMINDA UDAYA (1)· patent assignee history
2018Based in Woodland Hills, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SUARIS PETER RAMYALALself32007–2014
CHOU NAN-CHI22007–2010
DING YUZHENG22007–2010
LIU LUNG-TIEN22007–2010
MADURAWE RAMINDA UDAYA12014
Locations
LocationPatentsSpan
Camas, Washington, US42001–2010
Danville, California, US22010–2014
Woodland Hills, California, US12018