Inventor

Belliappa M. Kuttanna

Inventor

Austin, TX, US

Overview

32→

Patents

1998–2019

Patent span

Physics

Primary field (CPC G)

Patents· 32 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing74%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%

G06TImage data processing or generation, in general5%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%

PatentTitleYear

10,181,171Sharing resources between a CPU and GPU2019 9,600,283'Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode'2017 9,164,764'Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode'2015 8,762,692'Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode'2014 8,719,612'Method, system and apparatus for low-power storage of processor context information'2014 8,669,990'Sharing resources between a CPU and GPU'2014 8,392,728'Reducing idle leakage power in an IC'2013 8,352,770'Method, system and apparatus for low-power storage of processor context information'2013 8,289,850'Interconnect bandwidth throttler'2012 8,050,177'Interconnect bandwidth throttler'2011 7,877,619'Power mode control method and circuitry'2011 7,451,295'Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues'2008 7,269,711'Methods and apparatus for address generation in processors'2007 7,111,153'Early data return indication mechanism'2006 6,526,485'Apparatus and method for bad address handling'2003 6,484,240'Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols'2002 6,470,435'Dual state rename recovery using register usage'2002 6,389,517'Maintaining snoop traffic throughput in presence of an atomic operation a first port for a first queue tracks cache requests and a second port for a second queue snoops that have yet to be filtered'2002 6,347,360'Apparatus and method for preventing cache data eviction during an atomic operation'2002 6,321,303'Dynamically modifying queued transactions in a cache memory system'2001 6,311,254'Multiple store miss handling in a cache memory memory system'2001 6,286,082'Apparatus and method to prevent overwriting of modified cache entries prior to write back'2001 6,269,427'Multiple load miss handling in a cache memory system'2001 6,073,212'Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags'2000 6,029,006'Data processor with circuit for regulating instruction throughput while powered and method of operation'2000 5,974,505'Method and system for reducing power consumption of a non-blocking cache within a data processing system'1999 5,909,697'Reducing cache misses by snarfing writebacks in non-inclusive memory systems'1999 5,897,654'Method and system for efficiently fetching from cache during a cache fill operation'1999 5,873,123'Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries'1999 5,787,479'Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation'1998 5,737,751'Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system'1998 5,721,867'Method and apparatus for executing single beat write store instructions during a cache store linefill operation'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2001Patents assigned to IBM (9)· patent assignee history

1998–2000Patents assigned to MOTOROLA INC (7)· patent assignee history

1998–2019Based in Austin, TX, US· patent location history

1999–2003Patents assigned to SUN MICROSYSTEMS INC (6)· patent assignee history

1999–2001Based in Sunnyvale, CA, US· patent location history

2002–2019Patents assigned to INTEL CORP (14)· patent assignee history

2011–2014Patents assigned to KUTTANNA BELLIAPPA M (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	14	2002–2019
IBM	9	1998–2001
MOTOROLA INC	7	1998–2000
SUN MICROSYSTEMS INC	6	1999–2003
KUTTANNA BELLIAPPA Mself	3	2011–2014

Locations

Location	Patents	Span
Austin, Texas, US	27	1998–2019
Sunnyvale, California, US	5	1999–2001