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Inventor

David Ovrutsky

Inventor
Charlotte, NC, US

Overview

30→
Patents
2010–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 30 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H01LSemiconductor devices12%
G02BOptical elements, systems or apparatus9%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation8%
B29DProducing particular articles from plastics or from substances in a plastic state6%
H04NPictorial communication, e.g. television5%
Y10TTechnical subjects covered by former us classification5%
B23KSoldering or unsoldering2%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
PatentTitleYear
11,063,159Methods for routing electrical interconnections and resultant structures202110,818,550Methods for singulation and packaging202010,409,041TIR imaging lens, image capturing system having the same, and associated methods20199,910,239'Wafer level optical elements and applications thereof'20189,899,353'Off-chip vias in stacked chips'20189,548,254'Packaged semiconductor chips with array'20179,070,678'Packaged semiconductor chips with array'20159,048,234'Off-chip vias in stacked chips'20159,030,745'Wafer level optical elements and applications thereof'20158,883,562'Reconstituted wafer stack packaging with after-applied pad extensions'20148,885,257'Focus compensation for optical elements and applications thereof'20148,848,301'Focus compensation for optical elements and applications thereof'20148,759,973'Microelectronic assemblies having compliancy and methods therefor'20148,704,347'Packaged semiconductor chips'20148,687,294'Recessed optical surfaces'20148,653,644'Packaged semiconductor chips with array'20148,569,876'Packaged semiconductor chips with array'20138,476,774'Off-chip VIAS in stacked chips'20138,461,672'Reconstituted wafer stack packaging with after-applied pad extensions'20138,422,138'Wafer level optical elements and applications thereof'20138,189,277'Recessed optical surfaces'20128,115,308'Microelectronic assemblies having compliancy and methods therefor'20128,076,788'Off-chip vias in stacked chips'20118,053,281'Method of forming a wafer level package'20117,936,062'Wafer level chip packaging'20117,935,568'Wafer-level fabrication of lidded chips with electrodeposited dielectric coating'20117,901,989'Reconstituted wafer level stacking'20117,807,508'Wafer-level fabrication of lidded chips with electrodeposited dielectric coating'20107,791,199'Packaged semiconductor chips'20107,749,886'Microelectronic assemblies having compliancy and methods therefor'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2018Patents assigned to TESSERA INC (17)· patent assignee history
2010–2013Based in Ashkelon, IL· patent location history
2010Based in Jerusalem, IL· patent location history
2011–2018Patents assigned to OVRUTSKY DAVID (15)· patent assignee history
2011–2014Patents assigned to OGANESIAN VAGE (7)· patent assignee history
2011–2014Patents assigned to HABA BELGACEM (6)· patent assignee history
2011–2021Based in Charlotte, NC, US· patent location history
2011–2018Based in San Jose, CA, US· patent location history
2012–2015Patents assigned to HUDDLESTON JEREMY (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TESSERA INC172010–2018
OVRUTSKY DAVIDself152011–2018
OGANESIAN VAGE72011–2014
HABA BELGACEM62011–2014
HUDDLESTON JEREMY42012–2015
Locations
LocationPatentsSpan
Charlotte, NC, US132011–2021
San Jose, California, US112011–2018
Ashkelon, IL52010–2013
Jerusalem, IL12010