Inventor
Jingyi Bai
Inventor
San Jose, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1044%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices13%
H01LSemiconductor devices9%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
PatentTitleYear
10,741,602Back side illuminated CMOS image sensor arrays20209,876,045Back side illuminated CMOS image sensor arrays20188,878,264'Global shutter pixel with improved efficiency'20148,673,787'Method to reduce charge buildup during high aspect ratio contact etch'20148,598,632'Integrated circuit having pitch reduced patterns relative to photoithography features'20138,207,576'Pitch reduced patterns relative to photolithography features'20128,129,093'Prevention of photoresist scumming'20128,123,968'Multiple deposition for integration of spacers in pitch multiplication process'20128,119,535'Pitch reduced patterns relative to photolithography features'20128,048,812'Pitch reduced patterns relative to photolithography features'20117,985,692'Method to reduce charge buildup during high aspect ratio contact etch'20117,884,022'Multiple deposition for integration of spacers in pitch multiplication process'20117,718,540'Pitch reduced patterns relative to photolithography features'20107,704,673'Prevention of photoresist scumming'20107,651,951'Pitch reduced patterns relative to photolithography features'20107,390,746'Multiple deposition for integration of spacers in pitch multiplication process'20087,344,975'Method to reduce charge buildup during high aspect ratio contact etch'20087,270,917'Prevention of photoresist scumming'20077,259,079'Methods for filling high aspect ratio trenches in semiconductor layers'20077,253,118'Pitch reduced patterns relative to photolithography features'20077,175,944'Prevention of photoresist scumming'20076,982,207'Methods for filling high aspect ratio trenches in semiconductor layers'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2014Patents assigned to MICRON TECHNOLOGY INC (12)· patent assignee history
2006–2014Based in Boise, ID, US· patent location history
2007–2020Based in San Jose, CA, US· patent location history
2010–2013Patents assigned to ROUND ROCK RES LLC (7)· patent assignee history
2012–2014Patents assigned to BAI JINGYI (7)· patent assignee history
2012–2014Patents assigned to SANDHU GURTEJ S (5)· patent assignee history
2012–2013Patents assigned to MENG SHUANG (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 12 | 2006–2014 |
| BAI JINGYIself | 7 | 2012–2014 |
| ROUND ROCK RES LLC | 7 | 2010–2013 |
| SANDHU GURTEJ S | 5 | 2012–2014 |
| MENG SHUANG | 4 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 15 | 2007–2020 |
| Boise, ID, US | 7 | 2006–2014 |