Inventor
Lai-Juh Chen
Inventor
Hsinchu, TW
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1037%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
B24BMachines, devices, or processes for grinding or polishing21%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G01BMeasuring length, thickness or similar linear dimensions3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H01LSemiconductor devices3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
11,127,833Method to improve HKMG contact resistance20216,281,115'Sidewall protection for a via hole formed in a photosensitive, low dielectric constant layer'20016,251,806'Method to improve the roughness of metal deposition on low-k material'20016,242,361'Plasma treatment to improve DUV photoresist process'20015,985,093'Chemical-mechanical polish (CMP) pad conditioner'19995,976,979'Sequential oxygen plasma treatment and chemical mechanical polish (CMP) planarizing method for forming planarized low dielectric constant dielectric layer'19995,873,769'Temperature compensated chemical mechanical polishing to achieve uniform removal rates'19995,872,043'Method of planarizing wafers with shallow trench isolation'19995,858,869'Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant polymers'19995,834,377'In situ method for CMP endpoint detection'19985,834,375'Chemical-mechanical polishing planarization monitor'19985,823,854'Chemical-mechanical polish (CMP) pad conditioner'19985,723,387'Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates'19985,681,425'Teos plasma protection technology'19975,647,952'Chemical/mechanical polish (CMP) endpoint method'19975,643,050'Chemical/mechanical polish (CMP) thickness monitor'19975,637,031'Electrochemical simulator for chemical-mechanical polishing (CMP)'19975,635,425'In-situ N.sub.2 plasma treatment for PE TEOS oxide deposition'19975,489,553'HF vapor surface treatment for the 03 teos gap filling deposition'19965,461,010'Two step etch back spin-on-glass process for semiconductor planarization'19955,453,406'Aspect ratio independent coating for semiconductor planarization using SOG'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2001Patents assigned to IND TECH RES INST (20)· patent assignee history
1995–2001Based in Hsinchu, TW· patent location history
2021Patents assigned to SEMICONDUCTOR MFG INT BEIJING CORP (1)· patent assignee history
2021Patents assigned to SEMICONDUCTOR MFG INT SHANGHAI CORP (1)· patent assignee history
2021Based in Shanghai, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IND TECH RES INST | 20 | 1995–2001 |
| SEMICONDUCTOR MFG INT BEIJING CORP | 1 | 2021 |
| SEMICONDUCTOR MFG INT SHANGHAI CORP | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 20 | 1995–2001 |
| Shanghai, CN | 1 | 2021 |