Inventor

Matthew S. Buynoski

Inventor

Palo Alto, CA, US

Overview

1986–2018

Patent span

Electricity

Primary field (CPC H)

Patents· 132 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices35%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

B82YSpecific uses or applications of nanostructures4%

G11CStatic stores4%

H10KOrganic electric solid-state devices4%

H10BElectronic memory devices2%

H10NElectric solid-state devices not otherwise provided for2%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

PatentTitleYear

10,147,877Method of forming controllably conductive oxide2018 9,461,247'Method of forming controllably conductive oxide'2016 8,946,020'Method of forming controllably conductive oxide'2015 8,368,219'Buried silicide local interconnect with sidewall spacers and method for making the same'2013 8,093,698'Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device'2012 8,084,770'Test structures for development of metal-insulator-metal (MIM) devices'2011 8,049,334'Buried silicide local interconnect with sidewall spacers and method for making the same'2011 8,044,387'Semiconductor device built on plastic substrate'2011 8,012,673'Processing a copolymer to form a polymer memory cell'2011 7,786,003'Buried silicide local interconnect with sidewall spacers and method for making the same'2010 7,679,134'FinFET device with multiple fin structures'2010 7,468,525'Test structures for development of metal-insulator-metal (MIM) devices'2008 7,468,296'Thin film germanium diode with low reverse breakdown'2008 7,432,557'FinFET device with multiple channels'2008 7,105,421'Silicon on insulator field effect transistor with heterojunction gate'2006 7,067,349'Ion path polymers for ion-motion memory'2006 7,035,141'Diode array architecture for addressing nanoscale resistive memory arrays'2006 7,029,958'Self aligned damascene gate'2006 6,992,004'Implanted barrier layer to improve line reliability and method of forming same'2006 6,979,642'Method of self-annealing conductive lines that separates grain size effects from alloy mobility'2005 6,977,389'Planar polymer memory device'2005 6,916,696'Method for manufacturing a memory element'2005 6,893,895'CuS formation by anodic sulfide passivation of copper surface'2005 6,872,644'Semiconductor device with non-compounded contacts, and method of making'2005 6,861,325'Methods for fabricating CMOS-compatible lateral bipolar junction transistors'2005 6,861,349'Method of forming an adhesion layer with an element reactive with a barrier layer'2005 6,852,586'Self assembly of conducting polymer for formation of polymer memory cell'2005 6,835,655'Method of implanting copper barrier material to improve electrical performance'2004 6,815,340'Method of forming an electroless nucleation layer on a via bottom'2004 6,803,267'Silicon containing material for patterning polymeric memory element'2004 6,787,458'Polymer memory device formed in via opening'2004 6,787,436'Silicide-silicon contacts for reduction of MOSFET source-drain resistances'2004 6,784,506'Silicide process using high K-dielectrics'2004 6,770,905'Implantation for the formation of CuX layer in an organic memory device'2004 6,765,303'FinFET-based SRAM cell'2004 6,764,912'Passivation of nitride spacer'2004 6,759,308'Silicon on insulator field effect transistor with heterojunction gate'2004 6,753,247'Method(s) facilitating formation of memory cell(s) and patterned conductive'2004 6,727,546'Self-aligned triple gate silicon-on-insulator (SOI) device'2004 6,724,087'Laminated conductive lines and methods of forming the same'2004 6,716,686'Method for forming channels in a finfet device'2004 6,716,684'Method of making a self-aligned triple gate silicon-on-insulator device'2004 6,709,982'Double spacer FinFET formation'2004 6,710,452'Coherent diffusion barriers for integrated circuit interconnects'2004 6,703,307'Method of implantation after copper seed deposition'2004 6,703,308'Method of inserting alloy elements to reduce copper diffusion and bulk diffusion'2004 6,667,552'Low dielectric metal silicide lined interconnection system'2003 6,660,608'Method for manufacturing CMOS device having low gate resistivity using aluminum implant'2003 6,645,797'Method for forming fins in a FinFET device using sacrificial carbon layer'2003 6,642,590'Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process'2003 6,624,476'Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating'2003 6,624,037'XE preamorphizing implantation'2003 6,613,643'Structure, and a method of realizing, for efficient heat removal on SOI'2003 6,605,513'Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing'2003 6,602,781'Metal silicide gate transistors'2003 6,589,866'Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process'2003 6,583,012'Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes'2003 6,562,718'Process for forming fully silicided gates'2003 6,559,051'Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors'2003 6,552,395'Higher thermal conductivity glass for SOI heat removal'2003 6,544,872'Dopant implantation processing for improved source/drain interface with metal silicides'2003 6,534,379'Linerless shallow trench isolation method'2003 6,534,822'Silicon on insulator field effect transistor with a double Schottky gate structure'2003 6,528,362'Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process'2003 6,518,185'Integration scheme for non-feature-size dependent cu-alloy introduction'2003 6,518,113'Doping of thin amorphous silicon work function control layers of MOS gate electrodes'2003 6,518,167'Method of forming a metal or metal nitride interface layer between silicon nitride and copper'2003 6,518,154'Method of forming semiconductor devices with differently composed metal-based gate electrodes'2003 6,518,107'Non-arsenic N-type dopant implantation for improved source/drain interfaces with nickel silicides'2003 6,500,743'Method of copper-polysilicon T-gate formation'2002 6,495,887'Argon implantation after silicidation for improved floating-body effects'2002 6,492,258'METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY'2002 6,492,249'High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric'2002 6,492,209'Selectively thin silicon film for creating fully and partially depleted SOI on same wafer'2002 6,486,062'Selective deposition of amorphous silicon for formation of nickel silicide with smooth interface on N-doped substrate'2002 6,475,874'Damascene NiSi metal gate high-k transistor'2002 6,465,334'Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors'2002 6,465,309'Silicide gate transistors'2002 6,458,679'Method of making silicide stop layer in a damascene semiconductor structure'2002 6,452,250'Stacked integrated circuit and capacitor structure containing via structures'2002 6,440,867'Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process'2002 6,440,868'Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process'2002 6,436,840'Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process'2002 6,433,379'Tantalum anodization for in-laid copper metallization capacitor'2002 6,417,030'Leaky lower interface for reduction of floating body effect in SOI devices'2002 6,403,492'Method of manufacturing semiconductor devices with trench isolation'2002 6,396,108'Self-aligned double gate silicon-on-insulator (SOI) device'2002 6,392,280'Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process'2002 6,380,057'Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant'2002 6,376,336'Frontside SOI gettering with phosphorus doping'2002 6,376,343'Reduction of metal silicide/silicon interface roughness by dopant implantation processing'2002 6,368,950'Silicide gate transistors'2002 6,342,414'Damascene NiSi metal gate high-k transistor'2002 6,329,718'Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby'2001 6,326,247'Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer'2001 6,300,203'Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors'2001 6,297,157'Time ramped method for plating of high aspect ratio semiconductor vias and channels'2001 6,291,278'Method of forming transistors with self aligned damascene gate contact'2001 6,279,147'Use of an existing product map as a background for making test masks'2001 6,271,132'Self-aligned source and drain extensions fabricated in a damascene contact and gate process'2001 6,265,253'Aluminum disposable spacer to reduce mask count in CMOS transistor formation'2001 6,255,147'Silicon on insulator circuit structure with extra narrow field transistors and method of forming same'2001 6,248,658'Method of forming submicron-dimensioned metal patterns'2001 6,245,658'Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system'2001 6,246,118'Low dielectric semiconductor device with rigid, conductively lined interconnection system'2001 6,235,636'Resist removal by polishing'2001 6,232,048'Method for preparing narrow photoresist lines'2001 6,225,667'Leaky lower interface for reduction of floating body effect in SOI devices'2001 6,221,706'Aluminum disposable spacer to reduce mask count in CMOS transistor formation'2001 6,218,282'Method of forming low dielectric tungsten lined interconnection system'2001 6,207,553'Method of forming multiple levels of patterned metallization'2001 6,197,687'Method of patterning field dielectric regions in a semiconductor device'2001 6,194,299'Method for fabrication of a low resistivity MOSFET gate with thick metal on polysilicon'2001 6,191,012'Method for forming a shallow junction in a semiconductor device using antimony dimer'2001 6,190,985'Practical way to remove heat from SOI devices'2001 6,187,675'Method for fabrication of a low resistivity MOSFET gate with thick metal silicide on polysilicon'2001 6,180,441'Bar field effect transistor'2001 6,166,411'Heat removal from SOI devices by using metal substrates'2000 6,100,558'Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials'2000 6,087,208'Method for increasing gate capacitance by using both high and low dielectric gate material'2000 6,078,088'Low dielectric semiconductor device with rigid lined interconnection system'2000 5,970,330'Method of making field effect transistor with higher mobility'1999 5,932,911'Bar field effect transistor'1999 5,864,160'Transistor device with reduced hot carrier injection effects'1999 5,756,381'Method providing, an enriched source side extension and a lightly doped extension'1998 5,729,045'Field effect transistor with higher mobility'1998 5,043,292'Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures'1991 4,999,309'Aluminum-implant leakage reduction'1991 4,940,671'High voltage complementary NPN/PNP process'1990 4,910,160'High voltage complementary NPN/PNP process'1990 4,761,386'Method of fabricating conductive non-metallic self-passivating non-corrodable IC bonding pads'1988 4,622,576'Conductive non-metallic self-passivating non-corrodable IC bonding pads'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–1991Patents assigned to NAT SEMICONDUCTOR CORP (6)· patent assignee history

1986–2018Based in Palo Alto, CA, US· patent location history

1998–2013Patents assigned to ADVANCED MICRO DEVICES INC (114)· patent assignee history

2006–2015Patents assigned to SPANSION LLC (11)· patent assignee history

2011–2015Patents assigned to BUYNOSKI MATTHEW (3)· patent assignee history

2011–2012Patents assigned to AVANZINO STEVEN (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	114	1998–2013
SPANSION LLC	11	2006–2015
NAT SEMICONDUCTOR CORP	6	1986–1991
BUYNOSKI MATTHEWself	3	2011–2015
AVANZINO STEVEN	2	2011–2012

Locations

Location	Patents	Span
Palo Alto, California, US	132	1986–2018