Inventor
Sydney W. Poland
Inventor
Katy, TX, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing90%
G09GArrangements or circuits for control of indicating devices using static means to present variable information10%
PatentTitleYear
6,173,305'Division by iteration employing subtraction and conditional source selection of a prior difference or a left shifted remainder'20016,173,394'Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result'20016,116,768'Three input arithmetic logic unit with barrel rotator'20006,098,163'Three input arithmetic logic unit with shifter'20006,058,473'Memory store from a register pair conditional upon a selected status bit'20005,995,747'Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator'19995,995,748'Three input arithmetic logic unit with shifter and/or mask generator'19995,974,539'Three input arithmetic logic unit with shifter and mask generator'19995,961,635'Three input arithmetic logic unit with barrel rotator and mask generator'19995,761,726'Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor'19985,734,880'Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections'19985,696,954'Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input'19975,696,959'Memory store from a selected one of a register pair conditional upon the state of a selected status bit'19975,673,407'Data processor having capability to perform both floating point operations and memory access in response to a single instruction'19975,644,524'Iterative division apparatus, system and method employing left most one\'s detection and left most one\'s detection with exclusive or'19975,640,578'Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section'19975,634,065'Three input arithmetic logic unit with controllable shifter and mask generator'19975,600,847'Three input arithmetic logic unit with mask generator'19975,596,519'Iterative division apparatus, system and method employing left most one\'s detection and left most one\'s detection with exclusive OR'19975,590,350'Three input arithmetic logic unit with mask generator'19965,560,030'Transfer processor with transparency'19965,493,646'Pixel block transfer with transparency'19965,487,146'Plural memory access address generation employing guide table entries forming linked list'19965,442,581'Iterative division apparatus, system and method forming plural quotient bits per iteration'19954,298,949'Electronic calculator system having high order math capability'1981RE030671'Microprocessor system having high order capability'19814,153,937'Microprocessor system having high order capability'19794,139,893'Calculator program security system'1979Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1979–2001Patents assigned to TEXAS INSTRUMENTS INC (27)· patent assignee history
1979–1981Based in Arlington, TX, US· patent location history
1995–2001Based in Katy, TX, US· patent location history
1998–2000Based in Kary, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 27 | 1979–2001 |
Locations
| Location | Patents | Span |
|---|---|---|
| Katy, Texas, US | 19 | 1995–2001 |
| Kary, Texas, US | 5 | 1998–2000 |
| Arlington, Texas, US | 4 | 1979–1981 |