Inventor

Abhishek Venkatesh

Inventor

Hillsboro, OR, US

Overview

33→

Patents

2017–2021

Patent span

Physics

Primary field (CPC G)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Tprimary

G06TImage data processing or generation, in general63%

G06FElectric digital data processing25%

G09GArrangements or circuits for control of indicating devices using static means to present variable information4%

H04NPictorial communication, e.g. television4%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%

PatentTitleYear

11,132,759Mutli-frame renderer2021 11,107,444Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology2021 11,062,506Tile-based immediate mode rendering with early hierarchical-z2021 10,964,087Leveraging control surface fast clears to optimize 3D operations2021 10,937,126Tile-based multiple resolution rendering of images2021 10,930,060Conditional shader for graphics2021 10,867,427Multi-resolution image plane rendering within an improved graphics processor microarchitecture2020 10,861,126Asynchronous execution mechanism2020 10,803,656Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method2020 10,796,397Facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance at computing devices2020 10,783,603Graphics processor with tiled compute kernels2020 10,748,238Frequent data value compression for graphics processing units2020 10,733,690GPU mixed primitive topology type processing2020 10,728,492Synergistic temporal anti-aliasing and coarse pixel shading technology2020 10,706,591Controlling coarse pixel size from a stencil buffer2020 10,706,612Tile-based immediate mode rendering with early hierarchical-z2020 10,643,374Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer2020 10,573,066Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method2020 10,540,260Dynamic instruction latency management in SIMD machines2020 10,522,113Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology2019 10,521,271Hybrid low power homogenous grapics processing units2019 10,453,241Multi-resolution image plane rendering within an improved graphics processor microarchitecture2019 10,445,923Leveraging control surface fast clears to optimize 3D operations2019 10,262,388Frequent data value compression for graphics processing units2019 10,242,494Conditional shader for graphics2019 10,235,735Graphics processor with tiled compute kernels2019 10,229,468Automated conversion of GPGPU workloads to 3D pipeline workloads2019 10,204,394Multi-frame renderer2019 10,192,351Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method2019 10,163,179Method and apparatus for intelligent cloud-based graphics updates2018 10,134,170Stereoscopic rendering using vertix shader instancing2018 10,109,078Controlling coarse pixel size from a stencil buffer2018 9,563,930'Techniques for clearing a shared surface'2017

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2017–2021Patents assigned to INTEL CORP (33)· patent assignee history

2017–2021Based in Hillsboro, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	33	2017–2021

Locations

Location	Patents	Span
Hillsboro, OR, US	33	2017–2021