Inventor
Nikolaos Papandreou
Inventor
Thalwil, CH
Overview
Patents· 105 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores44%
G06FElectric digital data processing42%
H03MCoding12%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
11,126,360Dynamically adjusting block mode pool sizes202111,119,855Selectively storing parity data in different types of memory202111,120,882Error recovery of data in non-volatile memory during read202111,094,383Selective page calibration based on hierarchical page mapping202111,086,565Reducing effects of read array operations of read apparent voltage202111,086,705Managing the reliability of pages in non-volatile random access memory202111,056,199Updating corrective read voltage offsets in non-volatile random access memory202111,048,571Selectively performing multi-plane read operations in non-volatile memory202111,036,415Managing memory block calibration based on priority levels202111,023,150Block mode toggling using hybrid controllers202111,016,693Block health estimation for wear leveling in non-volatile memories202110,997,084Virtual to physical translation and media repair in storage class memory202110,977,181Data placement in write cache architecture supporting read heat data separation202110,956,049Wear-aware block mode conversion in non-volatile memory202110,957,407Calculating corrective read voltage offsets in non-volatile random access memory202110,956,317Garbage collection in non-volatile memory that fully programs dependent layers in a target block202110,942,808Adaptive data and parity placement using compression ratios of storage devices202110,942,662Relocating and/or re-programming blocks of storage space based on calibration frequency and resource utilization202110,937,512Managing programming errors in NAND flash memory202110,936,205Techniques for retention and read-disturb aware health binning202110,929,069Addressing page-correlated read issues using intra-block parity202110,824,352Reducing unnecessary calibration of a memory unit for which the error count margin has been exceeded202010,783,024Reducing block calibration overhead using read error triage202010,732,846Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory202010,699,791Adaptive read voltage threshold calibration in non-volatile memory202010,700,702Updating prefix codes for pseudo-dynamic data compression202010,658,054Methods for read threshold voltage shifting in non-volatile memory202010,656,847Mitigating asymmetric transient errors in non-volatile memory by proactive data relocation202010,614,881Calibration of open blocks in NAND flash memory202010,615,824Diagonal anti-diagonal memory structure202010,552,063Background mitigation reads in a non-volatile memory system202010,489,086Reducing read errors by performing mitigation reads to blocks of non-volatile memory201910,459,839Accelerating garbage collection of flushed logical erase blocks in non-volatile memory201910,453,537Techniques for reducing read voltage threshold calibration in non-volatile memory201910,417,088Data protection techniques for a non-volatile memory array201910,395,734Method and apparatus for determining a cell state of a resistive memory cell201910,348,334Reducing a decoding error floor by post-processing codewords encoded by binary symmetry-invariant product codes201910,268,537Initializing a pseudo-dynamic data compression system with predetermined history data typical of actual data201910,236,067State-dependent read voltage threshold adaptation for nonvolatile memory201910,222,997Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory201910,222,998Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory201910,176,867Estimation of level-thresholds for memory cells201910,170,195Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads201910,162,700Workload-adaptive data packing algorithm201810,128,871Diagonal anti-diagonal memory structure201810,115,472Reducing read disturb effect on partially programmed blocks of non-volatile memory201810,101,931Mitigating read errors following programming in a multi-level non-volatile memory201810,042,699Multi-chip device and method for storing data201810,037,803Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance value and a reference resistance value20189,996,420Error-correction encoding and decoding20189,996,418Error-correction encoding and decoding20189,990,279Page-level health equalization20189,953,706Method and apparatus for faster determination of cell state of a resistive memory cell using a parallel resistor20189,928,923'Estimation of level-thresholds for memory cells'20189,891,988'Device and method for storing data in a plurality of multi-level cell memory chips'20189,864,523'Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory'20189,865,340'Enhanced temperature compensation for resistive memory cell circuits'20189,793,929'Data packing for compression-enabled storage systems'20179,734,010'Data encoding in solid-state storage apparatus'20179,734,012'Data encoding in solid-state storage devices'20179,712,190'Data packing for compression-enabled storage systems'20179,672,921'Device and method for storing data in a plurality of multi-level cell memory chips'20179,672,910'Memory architecture for storing data in a plurality of memory chips'20179,666,273'Determining a cell state of a resistive memory cell'20179,647,694'Diagonal anti-diagonal memory structure'20179,639,462'Device for selecting a level for at least one read voltage'20179,619,328'Read-detection in multi-level cell memory'20179,588,702'Adapting erase cycle parameters to promote endurance of a memory'20179,583,184'Estimation of level-thresholds for memory cells'20179,583,205'Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory'20179,576,650'Read measurement of a plurality of resistive memory cells for alleviating resistance and current drift'20179,576,655'Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance value and a reference resistance value'20179,558,107'Extending useful life of a non-volatile memory by health grading'20179,558,817'Conditioning phase change memory cells'20179,524,775'Correlation detector'20169,520,189'Enhanced temperature compensation for resistive memory cell circuits'20169,513,813'Determining prefix codes for pseudo-dynamic data compression utilizing clusters formed based on compression ratio'20169,502,138'Data encoding in solid-state storage apparatus'20169,496,043'Dynamically optimizing flash data retention or endurance based on data write frequency'20169,496,031'Method and apparatus for faster determination of a cell state of a resistive memory cell using a parallel resistor'20169,477,540'Multi-stage codeword detector'20169,466,364'Correlation detector'20169,343,148'Method and apparatus for faster determination of a cell state of a resistive memory cell using a parallel resistor'20169,305,639'Read-detection in multi-level cell memory'20169,256,375'Level placement in solid-state memory'20169,251,909'Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory'20169,245,618'Read measurement of resistive memory cells'20169,236,120'Read measurement of resistive memory cells'20169,202,580'Level-estimation in multi-level cell memory'20159,190,171'Method and apparatus for read measurement of a plurality of resistive memory cells'20159,070,438'Programming of phase-change memory cells'20159,064,571'Programming at least one multi-level phase change memory cell'20159,059,744'Encoding a data word for writing the encoded data word in a multi-level solid state memory'20159,047,179'Level placement in solid-state memory'20158,972,837'Read/write operations in solid-state storage devices'20158,938,665'Read-detection in solid-state storage devices'20158,930,803'Detecting codewords in solid-state storage devices'20158,839,076'Encoding a data word for writing the encoded data word in a multi-level solid state memory'20148,780,611'Determining cell-state in phase-change memory'20148,755,214'Determining cell-state in phase-change memory'20148,578,246'Data encoding in solid-state storage devices'20138,446,760'Multilevel programming of phase change memory'20138,446,759'Multilevel programming of phase change memory'20138,441,847'Programming multi-level phase change memory cells'20138,351,251'Multilevel programming of phase change memory'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2021Patents assigned to IBM (100)· patent assignee history
2013–2015Patents assigned to PAPANDREOU NIKOLAOS (8)· patent assignee history
2013–2015Patents assigned to POZIDIS CHARALAMPOS (7)· patent assignee history
2013–2015Patents assigned to PANTAZI ANGELIKI (5)· patent assignee history
2013–2015Patents assigned to SEBASTIAN ABU (4)· patent assignee history
2013–2021Based in Thalwil, CH· patent location history
2013–2019Based in Zurich, CH· patent location history
2015–2019Based in Rueschlikon, CH· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 100 | 2013–2021 |
| PAPANDREOU NIKOLAOSself | 8 | 2013–2015 |
| POZIDIS CHARALAMPOS | 7 | 2013–2015 |
| PANTAZI ANGELIKI | 5 | 2013–2015 |
| SEBASTIAN ABU | 4 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Thalwil, CH | 77 | 2013–2021 |
| Rueschlikon, CH | 18 | 2015–2019 |
| Zurich, CH | 10 | 2013–2019 |