Inventor
Hugo W. K. Chan
Inventor
Fremont, CA, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
Y10Sprimary
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests34%
H10NElectric solid-state devices not otherwise provided for23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10DInorganic electric semiconductor devices7%
G11CStatic stores5%
H10BElectronic memory devices4%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light2%
H03FAmplifiers2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
PatentTitleYear
6,920,528'Smart memory'20056,681,287'Smart memory'20046,352,741'Planar high temperature superconductive integrated circuits for using ion implantation'20026,335,108'Implant-patterned superconductive device and a method for indirect ion implantation of superconductive films'20026,188,919'Using ion implantation to create normal layers in superconducting-normal-superconducting Josephson junctions'20016,147,032'Method for indirect Ion implantation of oxide superconductive films'20006,066,600'Method of making high-T.sub.c SSNS and SNS Josephson junction'20006,051,440'Method of fabricating a low-inductance in-line resistor for superconductor integrated circuits'20005,912,503'Planar in-line resistors for superconductor circuits'19995,892,243'High-temperature SSNS and SNS Josephson junction and method of making junction'19995,872,731'Multi-state Josephson memory'19995,863,868'Superconductive quantum interference device for digital logic circuits'19995,780,314'Method of forming a high performance low thermal loss bi-temperature superconductive device'19985,773,875'High performance, low thermal loss, bi-temperature superconductive device'19985,578,226'Multi-layered superconductive interconnects'19965,436,451'High-speed gamma pulse suppression circuit for semiconductor infrared detectors'19955,311,020'Monolithically-integrated semiconductor/superconductor infrared detector and readout circuit'19945,286,336'Submicron Josephson junction and method for its fabrication'19944,892,844'Making a low resistance three layered contact for silicon devices'19904,796,081'Low resistance metal contact for silicon devices'19894,762,805'Nitride-less process for VLSI circuit device isolation'19884,727,045'Plugged poly silicon resistor load for static random access memory cells'19884,693,925'Integrated circuit structure having intermediate metal silicide layer'19874,581,815'Integrated circuit structure having intermediate metal silicide layer and method of making same'19864,569,122'Method of forming a low resistance quasi-buried contact'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–1990Patents assigned to ADVANCED MICRO DEVICES INC (7)· patent assignee history
1986–2005Based in Fremont, CA, US· patent location history
1994–2002Patents assigned to TRW INC (16)· patent assignee history
1994–2002Based in Rancho Palos Verdes, CA, US· patent location history
1999–2000Based in Palos Verdes Estates, CA, US· patent location history
2004–2005Patents assigned to NANOAMP SOLUTIONS INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TRW INC | 16 | 1994–2002 |
| ADVANCED MICRO DEVICES INC | 7 | 1986–1990 |
| NANOAMP SOLUTIONS INC | 2 | 2004–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 12 | 1986–2005 |
| Rancho Palos Verdes, California, US | 11 | 1994–2002 |
| Palos Verdes Estates, California, US | 2 | 1999–2000 |