Inventor

Wei-Jen Hsia

Inventor

Sunnyvale, CA, US

Overview

1994–2008

Patent span

Electricity

Primary field (CPC H)

Patents· 36 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1043%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1038%

B23HWorking of metal by the action of a high concentration of electric current on a workpiece using an electrode which takes the place of a tool4%

C23CCoating metallic material4%

C23FNon-mechanical removal of metallic material from surface4%

C25FProcesses for the electrolytic removal of materials from objects4%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

PatentTitleYear

7,393,780'Dual layer barrier film techniques to prevent resist poisoning'2008 7,312,127'Incorporating dopants to enhance the dielectric properties of metal silicates'2007 7,259,462'Interconnect dielectric tuning'2007 7,220,362'Planarization with reduced dishing'2007 7,081,406'Interconnect dielectric tuning'2006 7,071,094'Dual layer barrier film techniques to prevent resist poisoning'2006 7,064,062'Incorporating dopants to enhance the dielectric properties of metal silicates'2006 7,029,591'Planarization with reduced dishing'2006 6,930,056'Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure'2005 6,881,664'Process for planarizing upper surface of damascene wiring structure for integrated circuit structures'2005 6,812,134'Dual layer barrier film techniques to prevent resist poisoning'2004 6,794,756'Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines'2004 6,790,784'Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure'2004 6,774,057'Method and structure for forming dielectric layers having reduced dielectric constants'2004 6,756,674'Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same'2004 6,686,272'Anti-reflective coatings for use at 248 nm and 193 nm'2004 6,613,665'Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface'2003 6,537,896'Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material'2003 6,528,423'PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL'2003 6,503,840'Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning'2003 6,492,731'Composite low dielectric constant film for integrated circuit structure'2002 6,423,630'Process for forming low K dielectric material between metal lines'2002 6,423,628'Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines'2002 6,420,277'Process for inhibiting crack formation in low dielectric constant dielectric films of integrated circuit structure'2002 6,346,490'Process for treating damaged surfaces of low k carbon doped silicon oxide dielectric material after plasma etching and plasma cleaning steps'2002 6,297,555'Method to obtain a low resistivity and conformity chemical vapor deposition titanium film'2001 6,232,658'Process to prevent stress cracking of dielectric films on semiconductor wafers'2001 6,204,192'Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures'2001 6,204,550'Method and composition for reducing gate oxide damage during RF sputter clean'2001 6,147,012'Process for forming low k silicon oxide dielectric material while suppressing pressure spiking and inhibiting increase in dielectric constant'2000 6,114,259'Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage'2000 5,994,211'Method and composition for reducing gate oxide damage during RF sputter clean'1999 5,895,267'Method to obtain a low resistivity and conformity chemical vapor deposition titanium film'1999 5,789,028'Method for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitride'1998 5,719,084'Method for the controlled formation of voids in doped glass dielectric films'1998 5,278,103'Method for the controlled formation of voids in doped glass dielectric films'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2006Patents assigned to LSI LOGIC CORP (32)· patent assignee history

1994–2008Based in Sunnyvale, CA, US· patent location history

2006–2007Based in Saratoga, CA, US· patent location history

2007–2008Patents assigned to LSI CORP (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
LSI LOGIC CORP	32	1994–2006
LSI CORP	4	2007–2008

Locations

Location	Patents	Span
Sunnyvale, California, US	30	1994–2008
Saratoga, California, US	6	2006–2007