Inventor
Rajesh Khamankar
Inventor
Coppell, TX, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices48%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
H10BElectronic memory devices7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
C23CCoating metallic material1%
PatentTitleYear
8,809,141'High performance CMOS transistors using PMD liner stress'20148,471,307'In-situ carbon doped e-SiGeCB stack for MOS transistor'20138,114,784'Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement'20128,084,787'PMD liner nitride films and fabrication methods for improved NMOS performance'20118,084,312'Nitrogen based implants for defect reduction in strained silicon'20118,021,990'Gate structure and method'20117,847,401'Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps'20107,682,988'Thermal treatment of nitrided oxide to improve negative bias thermal instability'20107,670,892'Nitrogen based implants for defect reduction in strained silicon'20107,601,575'Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance'20097,560,792'Reliable high voltage gate dielectric layers using a dual nitridation process'20097,553,718'Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps'20097,535,066'Gate structure and method'20097,514,308'CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers'20097,402,524'Post high voltage gate oxide pattern high-vacuum outgas surface treatment'20087,345,001'Gate dielectric having a flat nitrogen profile and method of manufacture therefor'20087,339,240'Dual-gate integrated circuit semiconductor device'20087,227,201'CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers'20077,226,834'PMD liner nitride films and fabrication methods for improved NMOS performance'20077,217,626'Transistor fabrication methods using dual sidewall spacers'20077,192,894'High performance CMOS transistors using PMD liner stress'20077,183,165'Reliable high voltage gate dielectric layers using a dual nitridation process'20077,129,127'Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation'20067,049,242'Post high voltage gate dielectric pattern plasma surface treatment'20067,018,925'Post high voltage gate oxide pattern high-vacuum outgas surface treatment'20067,012,028'Transistor fabrication methods using reduced width sidewall spacers'20066,956,267'Semiconductor with a nitrided silicon gate oxide and method'20056,930,007'Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance'20056,869,862'Method for improving a physical property defect value of a gate dielectric'20056,780,719'Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures'20046,730,566'Method for non-thermally nitrided gate formation for high voltage devices'20046,716,695'Semiconductor with a nitrided silicon gate oxide and method'20046,632,747'Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile'20036,610,614'Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates'20036,600,183'Integrated circuit capacitor and memory'20036,555,431'Method for forming integrated circuit capacitor and memory'20036,548,366'Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile'20036,503,846'Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates'20036,342,420'Hexagonally symmetric integrated circuit cell'20026,326,293'Formation of recessed polysilicon plugs using chemical-mechanical-polishing (CMP) and selective oxidation'20016,197,653'Capacitor and memory structure and method'20016,166,408'Hexagonally symmetric integrated circuit cell'20006,153,490'Method for forming integrated circuit capacitor and memory'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2014Patents assigned to TEXAS INSTRUMENTS INC (43)· patent assignee history
2000–2003Based in Irving, TX, US· patent location history
2003–2014Based in Coppell, TX, US· patent location history
2011–2014Patents assigned to BU HAOWEN (5)· patent assignee history
2011–2014Patents assigned to KHAMANKAR RAJESH (4)· patent assignee history
2011–2014Patents assigned to GRIDER DOUGLAS T (3)· patent assignee history
2011Patents assigned to CHAKRAVARTHI SRINIVASAN (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 43 | 2000–2014 |
| BU HAOWEN | 5 | 2011–2014 |
| KHAMANKAR RAJESHself | 4 | 2011–2014 |
| GRIDER DOUGLAS T | 3 | 2011–2014 |
| CHAKRAVARTHI SRINIVASAN | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Coppell, Texas, US | 36 | 2003–2014 |
| Irving, Texas, US | 7 | 2000–2003 |