Inventor
Ying Li
Inventor
Shanghai, CN
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing42%
H04WWireless communication networks15%
G11CStatic stores12%
H04LTransmission of digital information, e.g. telegraphic communication12%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use12%
G07CTime or attendance registers4%
G08GTraffic control systems4%
PatentTitleYear
10,986,678Methods and apparatus for device to device synchronization priority202110,973,003System and method for coverage enhancements of broadcast channels202110,966,165Adaptations of dual connectivity operation to UE capability202110,939,411System and method for coverage enhancements of broadcast channels202110,936,431Method, device and computer readable medium for restoring files202110,922,192Method, device and computer program product for data backup including determining a hardware configuration allocated to a proxy virtual machine based on a workload of a backup job202110,909,852Intelligent traffic safety pre-warning method, cloud server, onboard-terminal and system202110,852,956Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering202010,579,303Memory controller having command queue with entries merging202010,409,357Command-oriented low power control method of high-bandwidth-memory system201910,162,522Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy mode20189,881,664'Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device'20187,716,621'Method and system for improving signal integrity in integrated circuit designs'20105,974,245'Method and apparatus for making integrated circuits by inserting buffers into a netlist'19995,666,290'Interactive time-driven method of component placement that more directly constrains critical paths using net-based constraints'19975,638,291'Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997Patents assigned to VLSI TECHNOLOGY INC (2)· patent assignee history
1997–2010Based in San Jose, CA, US· patent location history
2010–2020Patents assigned to CADENCE DESIGN SYSTEMS INC (5)· patent assignee history
2018–2020Based in Shanghai, CN· patent location history
2020Patents assigned to CANDACE DESIGN SYSTEMS INC (1)· patent assignee history
2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (3)· patent assignee history
2021Patents assigned to EMC IP HOLDING CO LLC (2)· patent assignee history
2021Based in Richardson, TX, US· patent location history
2021Based in Chengdu, CN· patent location history
2021Based in Shandong, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 5 | 2010–2020 |
| SAMSUNG ELECTRONICS CO LTD | 3 | 2021 |
| EMC IP HOLDING CO LLC | 2 | 2021 |
| VLSI TECHNOLOGY INC | 2 | 1997 |
| CANDACE DESIGN SYSTEMS INC | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Shanghai, CN | 5 | 2018–2020 |
| Richardson, Texas, US | 4 | 2021 |
| San Jose, California, US | 4 | 1997–2010 |
| Chengdu, CN | 2 | 2021 |
| Shandong, CN | 1 | 2021 |