Inventor

DUN-NIAN YAUNG

Inventor

TW

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 117 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices34%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation22%

H10DInorganic electric semiconductor devices9%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

H04NPictorial communication, e.g. television3%

G02BOptical elements, systems or apparatus1%

H05KPrinted circuits1%

A61NElectrotherapy0%

H10KOrganic electric solid-state devices0%

PatentTitleYear

12,598,825Substrate contact in wafer backside2026 12,598,985Semiconductor structure and forming method thereof2026 12,581,764Bond structure having shielding structures for stacked IC chips2026 12,557,403High density image sensor2026 12,557,405Structure and method for backside-illuminated image device2026 12,532,560Isolation structure with multiple components to increase image sensor performance2026 12,525,528Metal-insulator-metal device with improved performance2026 12,507,490Semiconductor device including germanium region disposed in semiconductor substrate2025 12,490,538Stacked structure for CMOS image sensors2025 12,490,537Image sensor having an improved structure for small pixel designs2025 12,482,791Stacked integrated circuits with redistribution lines2025 12,476,2243DIC interconnect apparatus and method2025 12,463,181Multi-wafer integration2025 12,439,706Device over photodetector pixel sensor2025 12,424,605Hybrid bonding with uniform pattern density2025 12,408,466High-speed readout image sensor2025 12,396,2833DIC seal ring structure and methods of forming same2025 12,382,744Stacked substrate structure with inter-tier interconnection2025 12,381,195Semiconductor devices and methods of manufacture thereof2025 12,322,694Metal-insulator-metal device with improved performance2025 12,315,843Hybrid bonding technology for stacking integrated circuits2025 12,300,670Hybrid bond pad structure2025 12,283,564Semiconductor structure and manufacturing method thereof2025 12,278,250Semiconductor device including image sensor and method of forming the same2025 12,255,219Image sensor with overlap of backside trench isolation structure and vertical transfer gate2025 12,230,554Shield structure for backside through substrate vias (TSVs)2025 12,224,298Bond pad structure with high via density2025 12,218,164Semiconductor image-sensing structure and method for forming the same2025 12,218,165Semiconductor image sensor and method of manufacturing the same2025 12,218,106Backside contact to improve thermal dissipation away from semiconductor devices2025 12,218,166CSI with controllable isolation structure and methods of manufacturing and using the same2025 12,211,876Extra doped region for back-side deep trench isolation2025 12,205,868Oversized via as through-substrate-via (TSV) stop layer2025 12,191,336Image sensor having a gate dielectric structure for improved device scaling2025 12,176,370Stacked structure for CMOS image sensors including through-substrate-via contacting negative bias circuit2024 12,154,939High capacitance MIM device with self aligned spacer2024 12,154,927Semiconductor structure2024 12,148,782Composite BSI structure and method of manufacturing the same2024 12,148,781Image sensor device2024 12,142,569Integrated chip for standard logic performance improvement having a back-side through-substrate-via and method for forming the integrated chip2024 12,068,287Stacked semiconductor structure and method2024 12,062,679Backside structure for image sensor2024 12,057,446Stacked semiconductor device and method2024 12,040,336Semiconductor imaging device having improved dark current performance2024 12,033,919Backside or frontside through substrate via (TSV) landing on metal2024 12,034,037Backside capacitor techniques2024 12,009,214Gate electrodes with notches and methods for forming the same2024 11,996,433Pad structure for front side illuminated image sensor2024 11,996,399Hybrid bonding with uniform pattern density2024 11,984,465Multiple deep trench isolation (MDTI) structure for CMOS image sensor2024 11,978,758Methods and apparatus for via last through-vias2024 11,973,101Mechanisms for forming image-sensor device with deep-trench isolation structure2024 11,955,428Semiconductor structure and manufacturing method thereof2024 11,942,368Through silicon vias and methods of fabricating thereof2024 11,923,338Stacked integrated circuits with redistribution lines2024 11,915,977Interconnect structure for stacked device2024 11,916,043Multi-wafer integration2024 11,908,878Image sensor and manufacturing method thereof2024 11,901,388Device over photodetector pixel sensor2024 11,901,387Image sensor2024 11,901,396Back side illuminated image sensor with reduced sidewall-induced leakage2024 11,894,410Bond pad structure for bonding improvement2024 11,854,959Metal-insulator-metal device with improved performance2023 11,837,595Semiconductor device structure and method for manufacturing the same2023 11,817,470Stacked substrate structure with inter-tier interconnection2023 11,804,473Hybrid bond pad structure2023 11,798,9163DIC interconnect apparatus and method2023 11,791,357Composite BSI structure and method of manufacturing the same2023 11,791,332Stacked semiconductor device and method2023 11,791,361Image sensor with overlap of backside trench isolation structure and vertical transfer gate2023 11,769,791High capacitance MIM device with self aligned spacer2023 11,764,129Method of forming shield structure for backside through substrate vias (TSVS)2023 11,756,862Oversized via as through-substrate-via (TSV) stop layer2023 11,756,920Semiconductor structure and manufacturing method thereof2023 11,756,936Backside contact to improve thermal dissipation away from semiconductor devices2023 11,756,972Apparatus for reducing optical cross-talk in image sensors2023 11,728,366Extra doped region for back-side deep trench isolation2023 11,705,474Metal reflector grounding for noise reduction in light detector2023 11,705,449Through silicon via design for stacking integrated circuits2023 11,646,308Through silicon via design for stacking integrated circuits2023 11,646,247Ion through-substrate via2023 11,596,800Interconnect structure and method of forming same2023 11,600,653Methods and apparatus for via last through-vias2023 11,587,910Stacked semiconductor structure and method2023 11,552,027Semiconductor packaging device comprising a shield structure2023 11,538,837Semiconductor imaging device having improved dark current performance2022 11,532,6613DIC seal ring structure and methods of forming same2022 11,522,002Method for forming semiconductor image sensor2022 11,502,121Image sensor device2022 11,495,630Multiple deep trench isolation (MDTI) structure for CMOS image sensor2022 11,476,295Back side illuminated image sensor with reduced sidewall-induced leakage2022 11,456,176Gate electrodes with notches and methods for forming the same2022 11,437,420Image sensor with overlap of backside trench isolation structure and vertical transfer gate2022 11,430,823Method for manufacturing semiconductor image sensor device having deep trench isolation2022 11,424,228Semiconductor structure and method for manufacturing the same2022 11,410,972Hybrid bonding technology for stacking integrated circuits2022 11,404,534Backside capacitor techniques2022 11,387,167Semiconductor structure and manufacturing method for the same2022 11,342,374Mechanisms for forming image-sensor device with deep-trench isolation structure2022 11,342,373Manufacturing method of image sensing device2022 11,322,481Hybrid bonding technology for stacking integrated circuits2022 11,322,540Pad structure for front side illuminated image sensor2022 11,309,348High density image sensor2022 11,289,455Backside contact to improve thermal dissipation away from semiconductor devices2022 11,282,769Oversized via as through-substrate-via (TSV) stop layer2022 11,282,802Semiconductor device structure and method for forming the same2022 11,257,805Hybrid bonding with uniform pattern density2022 11,244,925Semiconductor device structure with back-side layer to reduce leakage2022 11,244,981Bond pad structure for bonding improvement2022 11,227,889Extra doped region for back-side deep trench isolation2022 11,222,814Integrated circuit (IC) structure for high performance and functional density2022 11,222,915Pad structure for front side illuminated image sensor2022 11,217,478Integrated circuit (IC) structure for high performance and functional density2022 11,211,419Composite bsi structure and method of manufacturing the same2021 11,177,307Stacked semiconductor dies with a conductive feature passing through a passivation layer2021 11,152,414Image sensor including dual isolation and method of making the same2021 11,139,367High density MIM capacitor structure2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (115)· patent assignee history

2021–2026Based in TW· patent location history

2026Patents assigned to TAIWAN SEMICONDUCTOR MFG COMPANY LTD (2)· patent assignee history

2026Patents assigned to TAIWAN SEMICONDUCTOR MANUFACUTURING COMPANY LTD (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	115	2021–2026
TAIWAN SEMICONDUCTOR MFG COMPANY LTD	2	2026
TAIWAN SEMICONDUCTOR MANUFACUTURING COMPANY LTD	1	2026

Locations

Location	Patents	Span
TW	117	2021–2026