Inventor
Shigeo Kawashima
Inventor
Kitakyusyu, JP
Overview
Patents· 3 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1043%
Y10TTechnical subjects covered by former us classification43%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
PatentTitleYear
5,545,922'Dual sided integrated circuit chip package with offset wire bonds and support block cavities'19965,527,740'Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities'19965,366,933'Method for constructing a dual sided, wire bonded integrated circuit chip package'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–1996Patents assigned to INTEL CORP (3)· patent assignee history
1994–1996Based in Kitakyusyu, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 3 | 1994–1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kitakyusyu, JP | 3 | 1994–1996 |