Inventor
Joseph P. Miller
Inventor
Cypress, TX, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing53%
H05KPrinted circuits13%
G02BOptical elements, systems or apparatus6%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein6%
H03KPulse technique6%
E04GScaffolding3%
H01RElectrically-conductive connections3%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
7,877,645'Use of operational configuration parameters to predict system failures'20117,299,380'Testing a receiver connected to a reference voltage signal'20077,073,078'Power control unit that provides one of a plurality of voltages on a common power rail'20066,717,821'Integrated circuit device/circuit board connection apparatus'20046,554,654'Multi-pin edge connector for circuit board'20036,456,502'Integrated circuit device/circuit board connection apparatus'20026,269,273'Delivering multiple optical signals using light that does not carry the data'20016,105,146'PCI hot spare capability for failed components'20006,070,253'Computer diagnostic board that provides system monitoring and permits remote terminal access'20006,032,271'Method and apparatus for identifying faulty devices in a computer system'20006,024,486'Data error detection and correction'20006,000,040'Method and apparatus for diagnosing fault states in a computer system'19995,938,751'Bus ring-back and voltage over-shoot reduction techniques coupled with hot-pluggability'19995,864,653'PCI hot spare capability for failed components'19995,861,764'Clock skew reduction using spider clock trace routing'19995,822,512'Switching control in a fault tolerant system'19985,822,571'Synchronizing data between devices'19985,809,186'Delivering multiple optical signals using light that does not carry the data'19985,797,018'Apparatus and method of preventing a deadlock condition in a computer system'19985,525,182'Apparatus and method for wet removal of floor tile'19965,406,590'Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits'19955,253,358'Cache memory expansion and transparent interconnection'19935,134,713'Coprocessor detection circuit'19925,097,532'Circuit for enabling a cache using a flush input to circumvent a late noncachable address input'19924,959,557'Negative feedback circuit to control the duty cycle of a logic system clock'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2002Patents assigned to COMPAQ COMPUTER CORP (18)· patent assignee history
1990–2001Based in Houston, TX, US· patent location history
1996Based in Neptune City, NJ, US· patent location history
1998Patents assigned to COMPAQ COMPUTER CORPORARTION (1)· patent assignee history
1998–2011Based in Cypress, TX, US· patent location history
2003–2011Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| COMPAQ COMPUTER CORP | 18 | 1990–2002 |
| HEWLETT PACKARD DEVELOPMENT CO | 5 | 2003–2011 |
| COMPAQ COMPUTER CORPORARTION | 1 | 1998 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cypress, Texas, US | 17 | 1998–2011 |
| Houston, Texas, US | 7 | 1990–2001 |
| Neptune City, New Jersey, US | 1 | 1996 |