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Inventor

John Susantha Fernando

Inventor
Coopersburg, PA, US

Overview

23→
Patents
1991–2019
Patent span
Physics
Primary field (CPC G)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing79%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
G11CStatic stores3%
H04BTransmission3%
PatentTitleYear
10,509,740Mutual exclusion in a non-coherent memory hierarchy201910,152,436Mutual exclusion in a non-coherent memory hierarchy20189,678,872'Memory paging for processors using physical addresses'20178,478,944'Method and apparatus for adaptive cache frame locking and unlocking'20138,261,022'Method and apparatus for adaptive cache frame locking and unlocking'20128,191,067'Method and apparatus for establishing a bound on the effect of task interference in a cache memory'20127,577,791'Virtualized load buffers'20097,533,232'Accessing data from different memory locations in the same cycle'20097,383,455'Method and apparatus for transferring multi-source/multi-sink control signals using a differential signaling technique'20087,353,513'Method and apparatus for establishing a bound on the effect of task interference in a cache memory'20087,346,735'Virtualized load buffers'20086,874,057'Method and apparatus for cache space allocation'20056,874,056'Method and apparatus for reducing cache thrashing'20056,754,748'Method and apparatus for distributing multi-source/multi-sink control signals among nodes on a chip'20046,434,163'Transverse correlator structure for a rake receiver'20026,397,240'Programmable accelerator for a programmable processor system'20026,272,616'Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths'20016,269,440'Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously'20016,052,766'Pointer register indirectly addressing a second register in the processor core of a digital processor'20005,805,489'Digital microprocessor device having variable-delay division hardware'19985,802,360'Digital microprocessor device having dnamically selectable instruction execution intervals'19985,761,492'Method and apparatus for uniform and efficient handling of multiple precise events in a processor by including event commands in the instruction set'19985,025,365'Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991Based in Los Angeles, CA, US· patent location history
1998–2000Patents assigned to LUCENT TECHNOLOGIES INC (4)· patent assignee history
1998–2013Based in Coopersburg, PA, US· patent location history
2001–2002Patents assigned to AGERE SYST GUARDIAN CORP (4)· patent assignee history
2004–2012Patents assigned to AGERE SYSTEMS INC (7)· patent assignee history
2008–2009Patents assigned to INTEL CORP (3)· patent assignee history
2008–2019Based in Austin, TX, US· patent location history
2012–2013Patents assigned to DWYER HARRY (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
AGERE SYSTEMS INC72004–2012
AGERE SYST GUARDIAN CORP42001–2002
LUCENT TECHNOLOGIES INC41998–2000
DWYER HARRY32012–2013
INTEL CORP32008–2009
Locations
LocationPatentsSpan
Coopersburg, Pennsylvania, US161998–2013
Austin, Texas, US62008–2019
Los Angeles, California, US11991