Inventor
Ghavam G. Shahidi
Inventor
Pound Ridge, NY, US
Overview
Patents· 361 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices22%
H01LSemiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation7%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution7%
Y02PClimate change mitigation technologies in the production or processing of goods4%
H10BElectronic memory devices2%
H10HInorganic light-emitting semiconductor devices having potential barriers2%
H10KOrganic electric solid-state devices1%
PatentTitleYear
11,132,177CMOS-compatible high-speed and low-power random number generator202111,094,843High voltage photovoltaics integrated with light emitting diode containing zinc oxide containing layer202111,094,842Heterojunction photovoltaic device and fabrication method202111,063,161Monolithically integrated high voltage photovoltaics with textured surface formed during the growth of wide bandgap materials202111,056,722Tool and method of fabricating a self-aligned solid state thin film battery202111,023,208True random number generator202111,024,754Focused energy photovoltaic cell202111,011,662Field-effect photovoltaic elements202110,997,321Encryption engine with an undetectable/tamper proof private key in late node CMOS technology202110,957,596Caterpillar trenches for efficient wafer dicing202110,957,252Active matrix OLED display with normally-on thin-film transistors202110,957,806Monolithically integrated high voltage photovoltaics with textured surface formed during the growth of wide bandgap materials202110,916,629Nanosheet-CMOS EPROM device with epitaxial oxide charge storage region202110,910,495Thin film transistors with epitaxial source/drain and drain field relief202110,903,208Distributed decoupling capacitor202110,884,918System implementation of one-time programmable memories202110,875,351Electrical component assembly on flexible materials202010,879,568Thin film lithium ion battery202010,804,366Integrated gate driver202010,772,720Method of assembling artificial electronic skin202010,770,614Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface202010,763,386Heterostructure germanium tandem junction solar cell202010,727,121Thin film interconnects with large grains202010,720,670Self-aligned 3D solid state thin film battery202010,707,367Contact for silicon heterojunction solar cells202010,700,211Thin film transistors with epitaxial source/drain contact regions202010,692,716Self-aligned spacerless thin film transistor202010,679,847Self-aligned spacerless thin film transistor202010,679,853Self-aligned, over etched hard mask fabrication method and structure202010,671,351Low-power random number generator202010,672,929Heterojunction photovoltaic device and fabrication method202010,651,252Vertically integrated active matrix backplane202010,644,184Type IV semiconductor based high voltage laterally stacked multijunction photovoltaic cell202010,615,290Normally-off junction field-effect transistors and application to complementary circuits202010,605,768Nanofluid sensor with real-time spatial sensing202010,608,111Thin film transistors with epitaxial source/drain and drain field relief202010,593,663Distributed decoupling capacitor202010,593,744Multiple subthreshold swing circuit and application to displays and sensors202010,587,224Low-power multi-stage amplifier for capacitive reading of low-amplitude and low-frequency signals202010,586,493Active matrix OLED display with normally-on thin-film transistors202010,580,925High voltage photovoltaics integrated with light emitting diode containing zinc oxide containing layer202010,573,558Caterpillar trenches for efficient wafer dicing202010,566,976Complementary logic circuit and application to thin-film hybrid electronics202010,559,641Multiple subthreshold swing circuit and application to displays and sensors202010,553,731Focused energy photovoltaic cell202010,541,343Monolithic integration of heterojunction solar cells202010,529,890Light emitting diode having improved quantum efficiency at low injection current202010,475,871Multiple subthreshold swing circuit and application to displays and sensors201910,424,605Integrated gate driver201910,423,805Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology201910,396,061Transparent electronics for invisible smart dust applications201910,391,805Electrical component assembly on flexible materials201910,388,814III-V solar cell structure with multi-layer back surface field201910,355,164Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface201910,347,599Terahertz detector comprised of p-n junction diode201910,304,985Heterojunction photovoltaic device and fabrication method201910,304,986Contact for silicon heterojunction solar cells201910,304,984Heterojunction photovoltaic device and fabrication method201910,304,988High voltage photovoltaics integrated with light emitting diode201910,283,663Heterostructure germanium tandem junction solar cell201910,283,463Terahertz detector comprised of P-N junction diode201910,276,739High voltage photovoltaics integrated with light emitting diode201910,262,991Distributed decoupling capacitor201910,256,365Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface201910,256,357Monolithic integration of heterojunction solar cells201910,249,783High voltage photovoltaics integrated with light emitting diode containing zinc oxide containing layer201910,249,782High voltage photovoltaics integrated with light emitting diode containing zinc oxide containing layer201910,224,430Thin film transistors with epitaxial source/drain and drain field relief201910,199,524Field-effect photovoltaic elements201910,177,266Contact for silicon heterojunction solar cells201910,170,361Thin film interconnects with large grains201910,141,461Textured multi-junction solar cell and fabrication method201810,128,452Hybrid junction field-effect transistor and active matrix structure201810,121,786FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers201810,115,833Self-aligned heterojunction field effect transistor201810,109,709P-FET with strained silicon-germanium channel201810,090,562Thin film lithium ion battery201810,090,415Thin film transistors with epitaxial source/drain contact regions201810,082,918In-cell capacitive touch and fingerprint detector201810,079,181P-FET with strained silicon-germanium channel201810,068,529Active matrix OLED display with normally-on thin-film transistors201810,050,166Silicon heterojunction photovoltaic device with wide band gap emitter201810,043,934Silicon-containing heterojunction photovoltaic element and device201810,043,941Light emitting diode having improved quantum efficiency at low injection current201810,038,104Normally-off junction field-effect transistors and application to complementary circuits201810,026,752Stacked SOI lateral bipolar transistor RF power amplifier and driver201810,011,920Low-temperature selective epitaxial growth of silicon for device integration201810,008,281One time programmable read-only memory (ROM) in SOI CMOS20189,991,408Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface20189,985,164Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface20189,968,438Method of fabricating artificial electronic skin20189,947,969Thin film lithium ion battery20189,935,230Type IV semiconductor based high voltage laterally stacked multijunction photovoltaic cell20189,935,223Monolithic integration of heterojunction solar cells20189,911,602'Embedded gallium-nitride in silicon'20189,911,739'III-V FinFET CMOS with III-V and germanium-containing channel closely spaced'20189,847,442Field-effect localized emitter photovoltaic device20179,812,599'Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys'20179,799,675'Strain engineering in back end of the line'20179,748,281'Integrated gate driver'20179,746,442'Switched-capacitor biosensor device'20179,741,871'Self-aligned heterojunction field effect transistor'20179,741,889'Contact for silicon heterojunction solar cells'20179,733,210'Nanofluid sensor with real-time spatial sensing'20179,716,201'Silicon heterojunction photovoltaic device with wide band gap emitter'20179,704,569'One time programmable read-only memory (ROM) in SOI CMOS'20179,687,181'Semiconductor device to be embedded within a contact lens'20179,685,329'Embedded gallium-nitride in silicon'20179,680,045'III-V solar cell structure with multi-layer back surface field'20179,673,190'ESD device compatible with bulk bias capability'20179,666,615'Semiconductor on insulator substrate with back bias'20179,627,378'Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding'20179,620,726'Hybrid junction field-effect transistor and active matrix structure'20179,589,848'FinFET structures having silicon germanium and silicon channels'20179,590,037'p-FET with strained silicon-germanium channel'20179,583,378'Formation of germanium-containing channel region by thermal condensation utilizing an oxygen permeable material'20179,577,065'Back-end transistors with highly doped low-temperature contacts'20179,570,485'Solar-powered energy-autonomous silicon-on-insulator device'20179,559,119'High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process'20179,543,290'Normally-off junction field-effect transistors and application to complementary circuits'20179,484,430'Back-end transistors with highly doped low-temperature contacts'20169,478,708'Embedded gallium—nitride in silicon'20169,478,658'Device and method for fabricating thin semiconductor channel and buried strain memorization layer'20169,478,651'Breakdown voltage multiplying integration scheme'20169,472,631'Flexible active matrix circuits for interfacing with biological tissue'20169,472,703'Monolithic integration of heterojunction solar cells'20169,472,607'Active matrix using hybrid integrated circuit and bipolar transistor'20169,466,651'Flexible active matrix display'20169,461,169'Device and method for fabricating thin semiconductor channel and buried strain memorization layer'20169,455,250'Distributed decoupling capacitor'20169,425,080'Non-volatile memory device employing semiconductor nanoparticles'20169,421,087'Artificial electronic skin'20169,406,717'Passivation of back-illuminated image sensor'20169,397,118'Thin-film ambipolar logic'20169,397,246'Monolithic integration of heterojunction solar cells'20169,391,094'Thin-film ambipolar logic'20169,391,180'Heterojunction bipolar transistors with intrinsic interlayers'20169,373,741'Heterostructure germanium tandem junction solar cell'20169,373,743'Silicon heterojunction photovoltaic device with wide band gap emitter'20169,373,691'Transistor with bonded gate dielectric'20169,368,420'Flexible, stretchable electronic devices'20169,356,019'Integrated circuit with on chip planar diode and CMOS devices'20169,343,616'Heterojunction light emitting diode'20169,337,196'III-V FinFET CMOS with III-V and germanium-containing channel closely spaced'20169,331,229'Heterojunction III-V solar cell performance'20169,324,566'Controlled spalling using a reactive material stack'20169,306,106'Monolithic integration of heterojunction solar cells'20169,293,476'Integrating active matrix inorganic light emitting diodes for display devices'20169,269,589'Dense finFET SRAM'20169,263,616'Selective emitter photovoltaic device'20169,252,324'Heterojunction light emitting diode'20169,245,903'High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process'20169,246,033'Contact for silicon heterojunction solar cells'20169,245,807'Integrated circuit with a thin body field effect transistor and capacitor'20169,240,355'On-chip diode with fully depleted semicondutor devices'20169,240,432'Passivation of back-illuminated image sensor'20169,231,146'Silicon photovoltaic element and fabrication method'20169,224,604'Device and method for forming sharp extension region with controllable junction depth and lateral overlap'20159,224,755'Flexible active matrix display'20159,219,187'Solar-powered energy-autonomous silicon-on-insulator device'20159,209,024'Back-end transistors with highly doped low-temperature contacts'20159,209,216'Passivation of back-illuminated image sensor'20159,166,072'Field-effect localized emitter photovoltaic device'20159,166,181'Hybrid junction field-effect transistor and active matrix structure'20159,136,402'High efficiency flexible solar cells for consumer electronics'20159,125,575'Flexible active matrix circuits for interfacing with biological tissue'20159,123,842'Photoreceptor with improved blocking layer'20159,105,775'Textured multi-junction solar cell and fabrication method'20159,105,518'Method of large-area circuit layout recognition'20159,099,585'Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys'20159,099,596'Heterojunction photovoltaic device and fabrication method'20159,093,533'FinFET structures having silicon germanium and silicon channels'20159,093,548'Thin film hybrid junction field effect transistor'20159,087,705'Thin-film hybrid complementary circuits'20159,087,772'Device and method for forming sharp extension region with controllable junction depth and lateral overlap'20159,070,795'III-V heterojunction light emitting diode'20159,070,788'Integrated circuit with a thin body field effect transistor and capacitor'20159,064,924'Heterojunction bipolar transistors with intrinsic interlayers'20159,064,717'Lock and key through-via method for wafer level 3D integration and structures produced thereby'20159,064,743'Flexible, stretchable electronic devices'20159,064,722'Breakdown voltage multiplying integration scheme'20159,059,014'Integrated circuit diode'20159,059,232'T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator'20159,059,007'Thin-film hybrid complementary circuits'20159,059,195'Lateral bipolar transistors having partially-depleted intrinsic base'20159,059,212'Back-end transistors with highly doped low-temperature contacts'20159,059,245'Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides'20159,059,096'Method to form silicide contact in trenches'20159,059,044'On-chip diode with fully depleted semiconductor devices'20159,059,231'T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator'20159,059,016'Lateral heterojunction bipolar transistors'20159,059,123'Active matrix using hybrid integrated circuit and bipolar transistor'20159,054,211'Compressively stressed FET device structures'20159,048,108'Integrated circuit with on chip planar diode and CMOS devices'20159,041,167'Radiation hardened SOI structure and method of making same'20159,035,431'Dense finFET SRAM'20159,018,517'Silicon heterojunction photovoltaic device with wide band gap emitter'20159,018,675'Heterojunction III-V photovoltaic cell fabrication'20159,006,071'Thin channel MOSFET with silicide local interconnect'20158,994,006'Non-volatile memory device employing semiconductor nanoparticles'20158,980,737'Methods of forming contact regions using sacrificial layers'20158,981,449'Extremely thin semiconductor on insulator (ETSOI) logic and memory hybrid chip'20158,969,938'Method and structure for forming on-chip high quality capacitors with ETSOI transistors'20158,969,992'Autonomous integrated circuits'20158,962,436'Lateral bipolar transistors having partially-depleted intrinsic base'20158,940,569'Dual-gate bio/chem sensor'20158,940,580'Textured multi-junction solar cell and fabrication method'20158,936,961'Removal of stressor layer from a spalled layer and method of making a bifacial solar cell using the same'20158,927,338'Flexible, stretchable electronic devices'20158,927,312'Method of fabricating MEMS transistors on far back end of line'20158,921,209'Defect free strained silicon on insulator (SSOI) substrates'20148,912,020'Integrating active matrix inorganic light emitting diodes for display devices'20148,912,424'Multi-junction photovoltaic device and fabrication method'20148,912,071'Selective emitter photovoltaic device'20148,912,529'Selective emitter photovoltaic device'20148,906,755'Active matrix using hybrid integrated circuit and bipolar transistor'20148,906,779'Solar-powered energy-autonomous silicon-on-insulator device'20148,900,936'FinFET device having reduce capacitance, access resistance, and contact resistance'20148,901,713'Extremely thin semiconductor-on-insulator with back gate contact'20148,891,266'Monolithic high voltage multiplier having high voltage semiconductor diodes and high-k capacitors'20148,890,247'Extremely thin semiconductor-on-insulator with back gate contact'20148,890,245'Raised source/drain structure for enhanced strain coupling from stress liner'20148,889,529'Heterojunction bipolar transistors with thin epitaxial contacts'20148,866,227'Thin semiconductor-on-insulator MOSFET with co-integrated silicon, silicon germanium and silicon doped with carbon channels'20148,865,530'Extremely thin semiconductor on insulator (ETSOI) logic and memory hybrid chip'20148,860,138'Strained thin body CMOS device having vertically raised source/drain stressors with single spacer'20148,853,038'Raised source/drain structure for enhanced strain coupling from stress liner'20148,853,040'Strained thin body CMOS device having vertically raised source/drain stressors with single spacer'20148,835,900'Highly scaled ETSOI floating body memory and memory circuit'20148,829,339'Field-effect inter-digitated back contact photovoltaic device'20148,822,320'Dense finFET SRAM'20148,815,684'Bulk finFET with super steep retrograde well'20148,809,164'Method of large-area circuit layout recognition'20148,809,168'Growing compressively strained silicon directly on silicon at low temperatures'20148,802,477'Heterojunction III-V photovoltaic cell fabrication'20148,778,448'Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys'20148,772,143'Field effect transistor devices with dopant free channels and back gates'20148,766,353'Tunnel field effect transistor'20148,766,377'Field effect transistor devices with dopant free channels and back gates'20148,765,577'Defect free strained silicon on insulator (SSOI) substrates'20148,748,258'Method and structure for forming on-chip high quality capacitors with ETSOI transistors'20148,742,504'Fully-depleted son'20148,710,588'Implant free extremely thin semiconductor devices'20148,658,444'Semiconductor active matrix on buried insulator'20148,659,066'Integrated circuit with a thin body field effect transistor and capacitor'20148,652,898'Integrated circuit with a thin body field effect transistor and capacitor'20148,642,378'Field-effect inter-digitated back contact photovoltaic device'20148,637,381'High-k dielectric and silicon nitride box region'20148,633,085'Dual-depth self-aligned isolation structure for a back gate electrode'20148,629,504'Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same'20148,624,104'Heterojunction III-V solar cell performance'20148,617,937'Forming narrow fins for finFET devices using asymmetrically spaced mandrels'20138,618,554'Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide'20138,617,971'Semiconductor substrates using bandgap material between III-V channel material and insulator layer'20138,614,447'Semiconductor substrates using bandgap material between III-V channel material and insulator layer'20138,610,212'Semiconductor active matrix on buried insulator'20138,610,233'Hybrid MOSFET structure having drain side schottky junction'20138,598,663'Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions'20138,592,323'Method of large-area circuit layout recognition'20138,587,086'Self-aligned dual depth isolation and method of fabrication'20138,574,970'Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drain'20138,552,487'SOI trench DRAM structure with backside strap'20138,546,228'Strained thin body CMOS device having vertically raised source/drain stressors with single spacer'20138,536,032'Formation of embedded stressor through ion implantation'20138,530,337'Method of large-area circuit layout recognition'20138,518,807'Radiation hardened SOI structure and method of making same'20138,513,723'Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chip'20138,513,765'Formation method and structure for a well-controlled metallic source/drain semiconductor device'20138,502,347'Bipolar junction transistor with epitaxial contacts'20138,492,839'Same-chip multicharacteristic semiconductor structures'20138,486,797'Bipolar junction transistor with epitaxial contacts'20138,482,078'Integrated circuit diode'20138,455,308'Fully-depleted SON'20138,404,540'Device and method of reducing junction leakage'20138,399,938'Stressed Fin-FET devices with low contact resistance'20138,399,957'Dual-depth self-aligned isolation structure for a back gate electrode'20138,394,710'Semiconductor devices fabricated by doped material layer as dopant source'20138,383,474'Thin channel device and fabrication method with a reverse embedded stressor'20138,368,053'Multilayer-interconnection first integration scheme for graphene and carbon nanotube transistor based integration'20138,361,889'Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator'20138,349,684'Semiconductor device with high K dielectric control terminal spacer structure'20138,343,819'Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same'20138,338,260'Raised source/drain structure for enhanced strain coupling from stress liner'20128,318,568'Tunnel field effect transistor'20128,318,574'SOI trench DRAM structure with backside strap'20128,304,301'Implant free extremely thin semiconductor devices'20128,293,615'Self-aligned dual depth isolation and method of fabrication'20128,278,175'Compressively stressed FET device structures'20128,263,468'Thin body semiconductor devices'20128,207,038'Stressed Fin-FET devices with low contact resistance'20128,202,767'Device and method of reducing junction leakage'20128,169,025'Strained CMOS device, circuit and method of fabrication'20128,169,024'Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation'20128,138,543'Hybrid FinFET/planar SOI FETs'20128,093,099'Lock and key through-via method for wafer level 3D integration and structures produced'20128,084,309'Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask'20118,080,838'Contact scheme for FINFET structures with multiple FINs'20118,053,759'Ion implantation for suppression of defects in annealed SiGe layers'20118,022,488'High-performance FETs with embedded stressors'20118,021,956'Ultrathin SOI CMOS devices employing differential STI liners'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2021Patents assigned to IBM (337)· patent assignee history
1998–2016Based in Yorktown Heights, NY, US· patent location history
2001–2007Based in Elmsford, NY, US· patent location history
2004–2021Based in Pound Ridge, NY, US· patent location history
2011–2019Patents assigned to SHAHIDI GHAVAM G (82)· patent assignee history
2011–2016Patents assigned to CHENG KANGGUO (48)· patent assignee history
2011–2016Patents assigned to DORIS BRUCE B (36)· patent assignee history
2012–2018Patents assigned to KHAKIFIROOZ ALI (49)· patent assignee history
2012–2015Based in Armonk, NY, US· patent location history
2013–2018Based in Ridge, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 337 | 1994–2021 |
| SHAHIDI GHAVAM Gself | 82 | 2011–2019 |
| KHAKIFIROOZ ALI | 49 | 2012–2018 |
| CHENG KANGGUO | 48 | 2011–2016 |
| DORIS BRUCE B | 36 | 2011–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Pound Ridge, New York, US | 279 | 2004–2021 |
| Yorktown Heights, New York, US | 36 | 1998–2016 |
| Ridge, New York, US | 31 | 2013–2018 |
| Elmsford, New York, US | 9 | 2001–2007 |
| Armonk, New York, US | 2 | 2012–2015 |