LexDanaLexDanabeta
Inventor

Tri-Rung Yew

Inventor
Hsinchu County, TW

Overview

89→
Patents
1998–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 89 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
H10DInorganic electric semiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10BElectronic memory devices12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
B82YSpecific uses or applications of nanostructures3%
H10KOrganic electric solid-state devices2%
H01LSemiconductor devices2%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution2%
C01BNon-metallic elements1%
PatentTitleYear
10,615,449Electrode material for secondary battery and secondary battery202010,079,277Method of fabricating metal-insulator-metal capacitor20189,662,026'Three-dimensional electrode and a biological probe comprising the same'20179,450,184'Multilayer-stacked resistive random access memory device'20168,937,241'Self-assembly nano-composite solar cell'20158,609,981'P-type transparent conductive oxide for solar cell comprising molybdenum trioxide doped with indium'20138,593,052'Microelectrode array and method for modifying carbon nanotube electrode interface of the same array'20138,461,037'Method for fabricating interconnections with carbon nanotubes'20138,368,057'Organic thin film transistor'20138,283,469'Perylene diimide derivative and organic semiconductor element using the same material'20127,858,147'Interconnect structure and method of fabricating the same'20107,807,979'Specimen kit and fabricating method thereof'20107,754,107'Carbon nanotube and method of visualizing carbon nanotube'20107,378,740'Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit'20087,067,917'Gradient barrier layer for copper back-end-of-line technology'20066,987,057'Method making bonding pad'20066,894,364'Capacitor in an interconnect system and method of manufacturing thereof'20056,794,752'Bonding pad structure'20046,680,248'Method of forming dual damascene structure'20046,593,223'Method of forming dual damascene structure'20036,479,344'Method of fabricating DRAM capacitor'20026,475,865'Method of fabricating semiconductor device'20026,403,411'Method for manufacturing lower electrode of DRAM capacitor'20026,361,929'Method of removing a photo-resist layer on a semiconductor wafer'20026,352,918'Method of forming inter-metal interconnection'20026,316,330'Method of fabricating a shallow trench isolation semiconductor device'20016,306,722'Method for fabricating shallow trench isolation structure'20016,291,288'Method of fabricating a thin and structurally-undefective dielectric structure for a storage capacitor in dynamic random-access memory'20016,291,295'Method of forming a storage electrode of a capacitor on an ion-implanted isolation layer'20016,281,143'Method of forming borderless contact'20016,265,313'Method of manufacturing copper interconnect'20016,265,780'Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit'20016,254,676'Method for manufacturing metal oxide semiconductor transistor having raised source/drain'20016,251,769'Method of manufacturing contact pad'20016,251,783'Method of manufacturing shallow trench isolation'20016,248,644'Method of fabricating shallow trench isolation structure'20016,242,334'Multi-step spacer formation of semiconductor devices'20016,238,972'Method for increasing capacitance'20016,235,606'Method of fabricating shallow trench isolation'20016,228,742'Method of fabricating shallow trench isolation structure'20016,221,746'Method for forming a poly gate structure'20016,221,712'Method for fabricating gate oxide layer'20016,221,744'Method for forming a gate'20016,218,238'Method of fabricating DRAM capacitor'20016,214,691'Method for forming shallow trench isolation'20016,191,028'Method of patterning dielectric'20016,184,142'Process for low k organic dielectric film etch'20016,180,492'Method of forming a liner for shallow trench isolation'20016,159,845'Method for manufacturing dielectric layer'20006,159,661'Dual damascene process'20006,153,466'Method for increasing capacitance'20006,150,251'Method of fabricating gate'20006,146,941'Method for fabricating a capacitor in a semiconductor device'20006,140,192'Method for fabricating semiconductor device'20006,133,086'Fabrication method of a tantalum pentoxide dielectric layer for a DRAM capacitor'20006,114,200'Method of fabricating a dynamic random access memory device'20006,087,262'Method for manufacturing shallow trench isolation structure'20006,083,789'Method for manufacturing DRAM capacitor'20006,084,304'Structure of metallization'20006,080,660'Via structure and method of manufacture'20006,077,769'Method of fabricating a daul damascene structure'20006,078,492'Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall'20006,069,066'Method of forming bonding pad'20006,060,379'Method of forming dual damascene structure'20006,057,189'Method of fabricating capacitor utilizing an ion implantation method'20006,037,206'Method of fabricating a capacitor of a dynamic random access memory'20006,027,994'Method to fabricate a dual metal-damascene structure in a substrate'20006,025,264'Fabricating method of a barrier layer'20006,020,258'Method for unlanded via etching using etch stop'20006,017,817'Method of fabricating dual damascene'20006,013,579'Self-aligned via process for preventing poison via formation'20006,013,555'Process for rounding an intersection between an HSG-SI grain and a polysilicon layer'20006,010,931'Planarization technique for DRAM cell capacitor electrode'20006,001,414'Dual damascene processing method'19996,001,733'Method of forming a dual damascene with dummy metal lines'19995,998,251'Process and structure for embedded DRAM'19995,994,183'Method for forming charge storage structure'19995,994,181'Method for forming a DRAM cell electrode'19995,990,015'Dual damascence process'19995,981,395'Method of fabricating an unlanded metal via of multi-level interconnection'19995,976,984'Process of making unlanded vias'19995,976,931'Method for increasing capacitance'19995,960,299'Method of fabricating a shallow-trench isolation structure in integrated circuit'19995,959,361'Dielectric pattern'19995,956,598'Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit'19995,930,618'Method of Making High-K Dielectrics for embedded DRAMS'19995,869,368'Method to increase capacitance'19995,801,094'Dual damascene process'19985,753,559'Method for growing hemispherical grain silicon'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2018Patents assigned to UNITED MICROELECTRONICS CORP (75)· patent assignee history
1998–2020Based in Hsinchu, TW· patent location history
1999–2006Based in Hsinchu County, TW· patent location history
2000Based in Hsin Chu, TW· patent location history
2001Based in Tu-Chen, TW· patent location history
2001Based in Hsin Chu Hsien, TW· patent location history
2010–2017Patents assigned to NAT UNIV TSING HUA (11)· patent assignee history
2012–2015Patents assigned to YEW TRI-RUNG (6)· patent assignee history
2012–2013Patents assigned to TING HENG-WEN (2)· patent assignee history
2013Patents assigned to SU HUAN-CHIEH (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
UNITED MICROELECTRONICS CORP751998–2018
NAT UNIV TSING HUA112010–2017
YEW TRI-RUNGself62012–2015
SU HUAN-CHIEH22013
TING HENG-WEN22012–2013
Locations
LocationPatentsSpan
Hsinchu County, TW531999–2006
Hsinchu, TW321998–2020
Tu-Chen, TW22001
Hsin Chu Hsien, TW12001
Hsin Chu, TW12000