Inventor
YEN-MING CHEN
Inventor
TW
Overview
Patents· 141 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices27%
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H10BElectronic memory devices5%
B82YSpecific uses or applications of nanostructures2%
H10NElectric solid-state devices not otherwise provided for2%
G11CStatic stores1%
G06FElectric digital data processing0%
H01GCapacitors0%
PatentTitleYear
12,568,681Active region patterning202612,550,697Different isolation liners for different type FinFETs and associated isolation feature fabrication202612,520,560Selective gate air spacer formation202612,501,601Method for forming different types of devices202512,484,292Methods of reducing parasitic capacitance in semicondutor devices202512,477,756Metal-insulator-metal structure and methods of fabrication thereof202512,453,161Semiconductor device with air-spacer202512,433,011Post gate dielectric processing for semiconductor device fabrication202512,426,346Semiconductor device and method202512,414,477Magnetic random access memory and manufacturing method thereof202512,408,363Semiconductor device with phosphorus-doped epitaxial features202512,406,952Chip structure with conductive layer202512,408,315Flexible merge scheme for source/drain epitaxy regions202512,400,429Method and electrical device for training cross-domain classifier202512,387,772Structure and method for MRAM devices with a slot via202512,389,612Method of forming a stress reduction structure for metal-insulator-metal capacitors202512,382,838Semiconductor memory device with spacer protection and method for forming same using multi-step patterning202512,382,692Dielectric inner spacers in multi-gate field-effect transistors202512,376,351Self-aligned contact air gap formation202512,374,655Method of forming package structure by using a wafer chuck with adjustable curved surface202512,369,366Convergent fin and nanostructure transistor structure and method202512,356,633Semiconductor devices and method of forming the same202512,356,647Epitaxial structures for fin-like field effect transistors202512,342,604Fin isolation structures of semiconductor devices202512,324,232Liner structures202512,324,201Integrated circuit device with source/drain barrier202512,302,611FinFET structure with a composite stress layer and reduced fin buckling202512,300,551Method for forming semiconductor structure202512,266,576Semiconductor device and methods of manufacture202512,266,655Transistors with recessed silicon cap and method forming same202512,266,592Through vias of semiconductor structure and method of forming thereof202512,249,531Method for forming semiconductor structure202512,249,640Conformal transfer doping method for Fin-like field effect transistor202512,218,138Air gap formation between gate spacer and epitaxy structure202512,183,697Semiconductor device having a metal pad and a protective layer for corrosion prevention due to exposure to halogen202412,171,091Multi-layer high-k gate dielectric structure202412,154,947Methods of forming epitaxial source/drain features in semiconductor devices202412,142,490Performing annealing process to improve Fin quality of a FinFET semiconductor202412,136,673Semiconductor device with self-aligned wavy contact profile and method of forming the same202412,136,658Integrated circuit with doped low-k sidewall spacers for gate stacks202412,107,165Semiconductor device structure with cap layer202412,094,950Nanostructures and method for manufacturing the same202412,082,510Magnetic tunnel junction device and method of forming the same202412,074,206Integrated circuit device with improved reliability202412,068,371Method for FinFET LDD doping202412,068,389Semiconductor device including gas spacers and method of manufacture202412,068,204Methods of forming epitaxial structures in fin-like field effect transistors202412,063,790Structure and method for MRAM devices202412,057,419Method for forming chip structure with conductive structure202412,051,628Semiconductor device with funnel shape spacer and methods of forming the same202412,041,760Multi-layer high-k gate dielectric structure202412,037,448Copolymer and method of manufacturing the same202412,027,574Resistor structure202412,020,988Fin field effect transistor (FinFET) device structure with dummy fin structure202412,022,643Multi-layer high-k gate dielectric structure202412,009,263Methods of reducing parasitic capacitance in semiconductor devices202412,004,431Structure and method for MRAM devices202412,002,863Semiconductor device with air-gap spacers202411,996,467Method for epitaxial growth and device202411,984,489Air spacer for a gate structure of a transistor202411,949,002Semiconductor device and method202411,937,515MRAM structure for balanced loading202411,923,405Metal-insulator-metal structure and methods of fabrication thereof202411,917,803Method for forming different types of devices202411,908,748Semiconductor devices and methods of forming the same202411,901,408Self-aligned contact air gap formation202411,894,421Integrated circuit device with source/drain barrier202411,862,713Conformal transfer doping method for fin-like field effect transistor202411,862,712Methods of semiconductor device fabrication including growing epitaxial features using different carrier gases202411,855,207FinFET structure and method with reduced fin buckling202311,855,022Shielding structures202311,856,743Flexible merge scheme for source/drain epitaxy regions202311,854,688Semiconductor device and method202311,855,097Air gap formation between gate spacer and epitaxy structure202311,848,230Different isolation liners for different type FinFETs and associated isolation feature fabrication202311,830,922Semiconductor device with air-spacer202311,824,121Semiconductor device with self-aligned wavy contact profile and method of forming the same202311,810,825Methods of forming epitaxial structures in fin-like field effect transistors202311,791,371Resistor structure202311,777,004Fin field effect transistor (FinFET) device structure and method for forming the same202311,769,820Methods of manufacturing a FinFET by forming a hollow area in the epitaxial source/drain region202311,744,084Semiconductor devices and method of forming the same202311,735,484Post gate dielectric processing for semiconductor device fabrication202311,735,648Epitaxial structures for fin-like field effect transistors202311,728,375Metal-insulator-metal (MIM) capacitor structure202311,728,344Hybrid SRAM design with nano-structures202311,728,223Semiconductor device and methods of manufacture202311,716,910MRAM structure for balanced loading202311,705,384Through vias of semiconductor structure and method of forming thereof202311,699,737Integrated circuit with doped low-k side wall spacers for gate spacers202311,694,933Methods of forming metal gate spacer202311,688,759Metal-insulator-metal capacitive structure and methods of fabricating thereof202311,688,794Method for epitaxial growth and device202311,677,028PMOS FinFET202311,670,608Prevention of metal pad corrosion due to exposure to halogen202311,631,746Semiconductor device and method of manufacture202311,626,505Dielectric inner spacers in multi-gate field-effect transistors202311,616,142Semiconductor device with self-aligned wavy contact profile and method of forming the same202311,610,841Interconnect structure for semiconductor device and methods of fabrication thereof202311,569,236Replacement gate process for FinFET202311,569,386Method for forming semiconductor device structure with cap layer202311,569,130Fin field effect transistor (FinFET) device structure with dummy Fin structure202311,538,927Nanostructures and method for manufacturing the same202211,532,695Stress reduction structure for metal-insulator-metal capacitors202211,508,736Method for forming different types of devices202211,508,827Air spacer for a gate structure of a transistor202211,502,182Selective gate air spacer formation202211,502,005Semiconductor devices and methods of forming the same202211,488,874Semiconductor device with funnel shape spacer and methods of forming the same202211,476,352Conformal transfer doping method for fin-like field effect transistor202211,477,573Handheld electronic device with multiple speakers202211,456,295Air gap formation between gate spacer and epitaxy structure202211,444,173Semiconductor device structure with salicide layer and method for forming the same202211,437,331Chip structure and method for forming the same202211,437,372Liner structures202211,411,107FinFET structure and method with reduced fin buckling202211,404,324Fin isolation structures of semiconductor devices202211,380,639Shielding structures202211,362,170Metal-insulator-metal (MIM) capacitor structure and method for forming the same202211,362,199Semiconductor device and method202211,355,400Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET202211,342,408Metal-insulator-metal structure and methods of fabrication thereof202211,302,535Performing annealing process to improve fin quality of a FinFET semiconductor202211,296,077Transistors with recessed silicon cap and method forming same202211,289,574Methods of forming epitaxial source/drain features in semiconductor devices202211,257,928Method for epitaxial growth and device202211,239,142Package structure and method for forming the same202211,222,857Method of forming a photoresist over a bond pad to mitigate bond pad corrosion202211,223,130Antenna structure202211,222,946Semiconductor device including a high density MIM capacitor and method202211,217,490Source/drain features with an etch stop layer202211,217,486Semiconductor device and method202211,205,724Self-aligned gate hard mask and method forming same202111,201,228Semiconductor device with air-spacer202111,195,951Semiconductor device with self-aligned wavy contact profile and method of forming the same202111,189,705Methods of reducing parasitic capacitance in multi-gate field-effect transistors202111,189,538Semiconductor structure with polyimide packaging and manufacturing method202111,177,211Method of manufacturing via structures of semiconductor devices202111,158,509Pattern fidelity enhancement with directional patterning technology202111,152,486FinFET semiconductor device having source/drain contact(s) separated by airgap spacer(s) from the gate stack(s) to reduce parasitic capacitance202111,145,564Multi-layer passivation structure and method2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (137)· patent assignee history
2021–2026Based in TW· patent location history
2022Patents assigned to ASUSTEK COMP INC (1)· patent assignee history
2022Patents assigned to CHILISIN ELECTRONICS CORP (1)· patent assignee history
2024Patents assigned to IND TECH RES INST (1)· patent assignee history
2025Patents assigned to NATIONAL SUN YAT SEN UNIVERSITY (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 137 | 2021–2026 |
| ASUSTEK COMP INC | 1 | 2022 |
| CHILISIN ELECTRONICS CORP | 1 | 2022 |
| IND TECH RES INST | 1 | 2024 |
| NATIONAL SUN YAT SEN UNIVERSITY | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 141 | 2021–2026 |