Inventor
Brian T. Vanderpool
Inventor
Byron, MN, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing56%
H04LTransmission of digital information, e.g. telegraphic communication35%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
G11CStatic stores2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
9,832,030Multicast packet routing via crossbar bypass paths20179,722,810'Computer-based flow synchronization for efficient multicast forwarding for products and services'20179,684,618'Peripheral component interconnect express (PCIe) ping in a switch-based environment'20179,678,906'Oldest link first arbitration between links grouped as single arbitration elements'20179,678,907'Oldest link first arbitration between links grouped as single arbitration elements'20179,667,564'Implementing hierarchical high radix switch with timesliced crossbar'20179,571,292'Multicast packet routing via crossbar bypass paths'20179,563,591'Peripheral component interconnect express (PCIe) ping in a switch-based environment'20179,479,455'Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar'20169,467,396'Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar'20169,455,926'Queue credit management'20169,444,758'Selective underflow protection in a network switch'20169,419,912'Selective underflow protection in a network switch'20169,336,169'Facilitating resource use in multicycle arbitration for single cycle data transfer'20169,323,703'Facilitating resource use in multicyle arbitration for single cycle data transfer'20169,207,999'Integrated link-based data recorder for semiconductor chip'20159,178,832'Queue credit management'20159,110,742'Integrated link-based data recorder for semiconductor chip'20158,984,206'Weightage-based scheduling for hierarchical switching fabrics'20158,902,899'Input buffered switching device including bypass logic'20148,897,301'Multicast bandwidth multiplication for a unified distributed switch'20148,879,553'Multicast bandwidth multiplication for a unified distributed switch'20148,812,793'Silent invalid state transition handling in an SMP environment'20148,195,892'Structure for silent invalid state transition handling in an SMP environment'20128,082,396'Selecting a command to send to memory'20118,010,682'Early coherency indication for return data in shared memory architecture'20117,890,708'Prioritization of out-of-order data transfers on shared data bus'20117,761,669'Memory controller granular read queue dynamic optimization of command selection'20107,650,259'Method for tuning chipset parameters to achieve optimal performance under varying workload types'20107,577,793'Patrol snooping for higher level cache eviction candidate identification'20097,536,514'Early return indication for read exclusive requests in shared memory architecture'20097,519,510'Derivative performance counter mechanism'20097,392,353'Prioritization of out-of-order data transfers on shared data bus'20087,010,654'Methods and systems for re-ordering commands to access memory'20066,836,831'Independent sequencers in a DRAM control structure'20046,801,982'Read prediction algorithm to provide low latency reads with SDRAM cache'20046,754,858'SDRAM address error detection method and apparatus'20045,781,773'Method for transforming and storing data for search and display and a searching system utilized therewith'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998Based in White Bear Township, MN, US· patent location history
2004–2017Patents assigned to IBM (36)· patent assignee history
2004–2006Based in Rochester, MN, US· patent location history
2008–2017Based in Byron, MN, US· patent location history
2011–2014Patents assigned to VANDERPOOL BRIAN T (4)· patent assignee history
2012–2014Patents assigned to KORNEGAY MARCUS L (2)· patent assignee history
2012–2014Patents assigned to PHAM NGAN N (2)· patent assignee history
2014Patents assigned to BASSO CLAUDE (1)· patent assignee history
2016Based in Bryon, MN, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 36 | 2004–2017 |
| VANDERPOOL BRIAN Tself | 4 | 2011–2014 |
| KORNEGAY MARCUS L | 2 | 2012–2014 |
| PHAM NGAN N | 2 | 2012–2014 |
| BASSO CLAUDE | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Byron, Minnesota, US | 32 | 2008–2017 |
| Rochester, Minnesota, US | 4 | 2004–2006 |
| Bryon, Minnesota, US | 1 | 2016 |
| White Bear Township, Minnesota, US | 1 | 1998 |