Inventor
Nancy M. Zelick
Inventor
Portland, OR, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H01LSemiconductor devices23%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H01BCables5%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%
H10HInorganic light-emitting semiconductor devices having potential barriers5%
H10KOrganic electric solid-state devices5%
H10NElectric solid-state devices not otherwise provided for5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
10,756,198Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same202010,304,929Two-dimensional condensation for uniaxially strained semiconductor fins201910,249,490Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy20199,865,684'Nanoscale structure with epitaxial film having a recessed bottom portion'20189,768,269'Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same'20179,711,598'Two-dimensional condensation for uniaxially strained semiconductor fins'20179,680,013'Non-planar device having uniaxially strained semiconductor body and method of making same'20179,640,537'Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy'20179,419,140'Two-dimensional condensation for uniaxially strained semiconductor fins'20169,391,181'Lattice mismatched hetero-epitaxial film'20169,159,835'Two-dimensional condensation for uniaxially strained semiconductor fins'20159,029,835'Epitaxial film on nanoscale structure'20158,878,363'Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same'20148,872,225'Defect transferred and lattice mismatched epitaxial film'20148,558,279'Non-planar device having uniaxially strained semiconductor body and method of making same'20138,334,184'Polish to remove topography in sacrificial gate layer prior to gate patterning'20128,211,772'Two-dimensional condensation for uniaxially strained semiconductor fins'20127,960,794'Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow'20117,348,284'Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2020Patents assigned to INTEL CORP (19)· patent assignee history
2008–2020Based in Portland, OR, US· patent location history
2012–2016Patents assigned to KAVALIEROS JACK T (5)· patent assignee history
2012–2016Patents assigned to CEA STEPHEN M (4)· patent assignee history
2012–2016Patents assigned to KUHN MARKUS (4)· patent assignee history
2012–2016Patents assigned to JIN BEEN-YIH (3)· patent assignee history
2014Based in Beaverton, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 19 | 2008–2020 |
| KAVALIEROS JACK T | 5 | 2012–2016 |
| CEA STEPHEN M | 4 | 2012–2016 |
| KUHN MARKUS | 4 | 2012–2016 |
| JIN BEEN-YIH | 3 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 18 | 2008–2020 |
| Beaverton, OR, US | 1 | 2014 |