Inventor

Wesley C. Natzle

Inventor

New Paltz, NY, US

Overview

1992–2016

Patent span

Electricity

Primary field (CPC H)

Patents· 66 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices33%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1032%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

G05BControl or regulating systems in general3%

H01LSemiconductor devices3%

H10BElectronic memory devices3%

Y02PClimate change mitigation technologies in the production or processing of goods3%

C23CCoating metallic material2%

C23FNon-mechanical removal of metallic material from surface2%

PatentTitleYear

9,263,276'High-k/metal gate transistor with L-shaped gate encapsulation layer'2016 9,252,018'High-k/metal gate transistor with L-shaped gate encapsulation layer'2016 8,900,961'Selective deposition of germanium spacers on nitride'2014 8,575,709'High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof'2013 8,492,803'Field effect device with reduced thickness gate'2013 8,318,565'High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof'2012 8,198,103'Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist'2012 7,955,926'Structure and method to control oxidation in high-k gate structures'2011 7,859,013'Metal oxide field effect transistor with a sharp halo'2010 7,851,299'Subgroundrule space for improved metal high-k device'2010 7,705,385'Selective deposition of germanium spacers on nitride'2010 7,567,700'Dynamic metrology sampling with wafer uniformity control'2009 7,502,660'Feature dimension deviation correction system, method and program product'2009 7,502,709'Dynamic metrology sampling for a dual damascene process'2009 7,498,271'Nitrogen based plasma process for metal gate MOS device'2009 7,470,629'Structure and method to fabricate finfet devices'2008 7,459,382'Field effect device with reduced thickness gate'2008 7,451,011'Process control using physical modules and virtual modules'2008 7,384,835'Metal oxide field effect transistor with a sharp halo and a method of forming the transistor'2008 7,344,965'Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gaseous additions'2008 7,344,983'Clustered surface preparation for silicide and metal contacts'2008 7,292,906'Formula-based run-to-run control'2007 7,289,864'Feature dimension deviation correction system, method and program product'2007 7,212,878'Wafer-to-wafer control using virtual modules'2007 7,211,496'Freestanding multiplayer IC wiring structure'2007 7,176,534'Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch'2007 7,077,903'Etch selectivity enhancement for tunable etch resistant anti-reflective layer'2006 7,049,662'Structure and method to fabricate FinFET devices'2006 6,960,510'Method of making sub-lithographic features'2005 6,926,843'Etching of hard masks'2005 6,905,941'Structure and method to fabricate ultra-thin Si channel devices'2005 6,884,734'Vapor phase etch trim structure with top etch blocking layer'2005 6,858,903'MOSFET device with in-situ doped, raised source and drain structures'2005 6,858,532'Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling'2005 6,849,153'Removal of post-rie polymer on A1/CU metal line'2005 6,841,831'Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process'2005 6,838,347'Method for reducing line edge roughness of oxide material using chemical oxide removal'2005 6,835,614'Damascene double-gate MOSFET with vertical channel regions'2004 6,790,733'Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer'2004 6,774,000'Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures'2004 6,660,598'Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region'2003 6,656,824'Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch'2003 6,635,923'Damascene double-gate MOSFET with vertical channel regions'2003 6,617,085'Wet etch reduction of gate widths'2003 6,353,249'MOSFET with high dielectric constant gate insulator and minimum overlap capacitance'2002 6,335,261'Directional CVD process with optimized etchback'2002 6,319,794'Structure and method for producing low leakage isolation devices'2001 6,271,094'Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance'2001 6,245,619'Disposable-spacer damascene-gate process for SUB 0.05 .mu.m MOS devices'2001 6,171,971'Freestanding multilayer wiring structure'2001 6,097,092'Freestanding multilayer IC wiring structure'2000 6,074,951'Vapor phase etching of oxide masked by resist or masking material'2000 6,071,815'Method of patterning sidewalls of a trench in integrated circuit manufacturing'2000 6,054,328'Method for cleaning the surface of a dielectric'2000 5,980,770'Removal of post-RIE polymer on Al/Cu metal line'1999 5,876,879'Oxide layer patterned by vapor phase etching'1999 5,838,055'Trench sidewall patterned by vapor phase etching'1998 5,838,045'Folded trench and RIE/deposition process for high-value capacitors'1998 5,792,275'Film removal by chemical transformation and aerosol clean'1998 5,766,971'Oxide strip that improves planarity'1998 5,665,622'Folded trench and rie/deposition process for high-value capacitors'1997 5,636,320'Sealed chamber with heating lamps provided within transparent tubes'1997 5,423,940'Supersonic molecular beam etching of surfaces'1995 5,286,331'Supersonic molecular beam etching of surfaces'1994 5,282,925'Device and method for accurate etching and removal of thin film'1994 5,081,439'Thin film resistor and method for producing same'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2016Patents assigned to IBM (62)· patent assignee history

1992–1995Based in Wappingers Falls, NY, US· patent location history

1997–2016Based in New Paltz, NY, US· patent location history

2007–2009Patents assigned to TOKYO ELECTRON LTD (6)· patent assignee history

2012–2016Patents assigned to NATZLE WESLEY C (7)· patent assignee history

2012–2013Patents assigned to BU HUIMING (2)· patent assignee history

2012–2013Patents assigned to CHUDZIK MICHAEL P (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	62	1992–2016
NATZLE WESLEY Cself	7	2012–2016
TOKYO ELECTRON LTD	6	2007–2009
BU HUIMING	2	2012–2013
CHUDZIK MICHAEL P	2	2012–2013

Locations

Location	Patents	Span
New Paltz, New York, US	62	1997–2016
Wappingers Falls, New York, US	4	1992–1995