Inventor
Prakash Math
Inventor
Portland, OR, US
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
10,409,611Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution201910,409,612Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution20198,516,577'Regulating atomic memory operations to prevent denial of service attack'20137,590,784'Detecting and resolving locks in a memory unit'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2019Patents assigned to INTEL CORP (4)· patent assignee history
2009Based in Hillsboro, OR, US· patent location history
2013Patents assigned to BAIR MICHAEL S (1)· patent assignee history
2013Patents assigned to BURNS DAVID W (1)· patent assignee history
2013Patents assigned to CHAPPELL ROBERT S (1)· patent assignee history
2013Patents assigned to MATH PRAKASH (1)· patent assignee history
2013–2019Based in Portland, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 4 | 2009–2019 |
| BAIR MICHAEL S | 1 | 2013 |
| BURNS DAVID W | 1 | 2013 |
| CHAPPELL ROBERT S | 1 | 2013 |
| MATH PRAKASHself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 3 | 2013–2019 |
| Hillsboro, OR, US | 1 | 2009 |