LexDanaLexDanabeta
Inventor

Kong-Beng Thei

Inventor
Hsinchu, TW

Overview

181→
Patents
2000–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 181 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices40%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H01LSemiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10BElectronic memory devices3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
G11CStatic stores1%
H01CResistors1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
11,133,226FUSI gated device formation202111,121,038Spacer structure and manufacturing method thereof202111,063,038Through silicon via design for stacking integrated circuits202111,018,241Polysilicon design for replacement gate technology202111,011,619Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices202111,004,844Recessed STI as the gate dielectric of HV device202110,991,693Boundary region for high-k-metal-gate (HKMG) integration technology202110,964,692Through silicon via design for stacking integrated circuits202110,950,708Dishing prevention dummy structures for semiconductor devices202110,937,785Semiconductor device202110,937,891Spacer structure and manufacturing method thereof202110,930,776High voltage LDMOS transistor and methods for manufacturing the same202110,916,542Recessed STI as the gate dielectric of HV device202110,879,200Sidewall spacer to reduce bond pad necking and/or redistribution layer necking202010,868,141Spacer structure and manufacturing method thereof202010,804,093Dishing prevention columns for bipolar junction transistors202010,804,220Dishing prevention columns for bipolar junction transistors202010,790,279High voltage integration for HKMG technology202010,790,387High voltage LDMOS transistor and methods for manufacturing the same202010,748,899Epitaxial source and drain structures for high voltage devices202010,665,510Spacer structure and manufacturing method thereof202010,658,492Polysilicon design for replacement gate technology202010,658,318Film scheme for bumping202010,629,592Through silicon via design for stacking integrated circuits202010,553,583Boundary region for high-k-metal-gate(HKMG) integration technology202010,535,752Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices202010,516,029Dishing prevention dummy structures for semiconductor devices201910,510,685Dishing prevention columns for bipolar junction transistors201910,510,750High voltage integration for HKMG technology201910,403,736Polysilicon design for replacement gate technology201910,347,757Lateral MOSFET201910,340,357Dishing prevention dummy structures for semiconductor devices201910,325,964OLED merged spacer device201910,297,491Semiconductor device having isolation structure in well of substrate201910,164,037Semiconductor device structure and method for forming the same201810,147,814Lateral MOSFET201810,096,523Spacer structure and manufacturing method thereof201810,084,061Polysilicon design for replacement gate technology201810,050,033High voltage integration for HKMG technology201810,014,291SiC crystalline on Si substrates to allow integration of GaN and Si electronics20189,929,251'Polysilicon design for replacement gate technology'20189,911,845'High voltage LDMOS transistor and methods for manufacturing the same'20189,887,134'Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices'20189,887,302'Schottky barrier diode'20189,871,105'Method of forming an isolation structure in a well of a substrate'20189,853,149Floating grid and crown-shaping poly for improving ILD CMP dishing20179,691,895'Lateral MOSFET'20179,685,395'Wiring layout having differently shaped vias'20179,679,988'Polysilicon design for replacement gate technology'20179,601,585'Transistor having a wing region'20179,502,585'Schottky barrier diode and method of manufacturing the same'20169,455,344'Integrated circuit metal gate structure having tapered profile'20169,437,494'Semiconductor arrangement and formation thereof'20169,419,099'Method of fabricating spacers in a strained semiconductor device'20169,362,272'Lateral MOSFET'20169,356,108'Dummy structure for multiple gate dielectric interface and methods'20169,349,655'Method for mechanical stress enhancement in semiconductor devices'20169,318,366'Method of forming integrated circuit having modified isolation structure'20169,299,806'High voltage drain-extended MOSFET having extra drain-OD addition'20169,263,396'Photo alignment mark for a gate last process'20169,117,840'Method of fabricating spacers in a strained semiconductor device'20159,099,556'Transistor having an active region with wing structure'20159,099,467'E-fuse structure design in electrical programmable redundancy for embedded memory circuit'20159,059,310'SRAM devices utilizing strained-channel transistors and methods of manufacture'20159,054,025'Process for controlling shallow trench isolation step height'20159,035,380'High voltage drain-extended MOSFET having extra drain-OD addition'20159,006,040'Systems and methods for fabricating semiconductor devices having larger die dimensions'20158,987,923'Semiconductor seal ring'20158,981,562'Wiring layout having differently shaped vias'20158,969,972'Modifying work function in PMOS devices by counter-doping'20158,972,912'Structure for chip extension'20158,970,015'Method for protecting a gate structure during contact formation'20158,932,951'Dishing-free gap-filling with multiple CMPs'20158,890,260'Polysilicon design for replacement gate technology'20148,847,319'Dummy structure for multiple gate dielectric interface and methods'20148,803,202'Layout methods of integrated circuits having unit MOS devices'20148,796,084'Method for removing hard masks on gates in semiconductor manufacturing process'20148,735,235'Integrated circuit metal gate structure and method of fabrication'20148,716,103'Semiconductor device and method of fabricating same'20148,673,712'Power transistor with high voltage counter implant'20148,669,153'Integrating a first contact structure in a gate last process'20148,648,446'Method for protecting a gate structure during contact formation'20148,629,050'E-fuse structure design in electrical programmable redundancy for embedded memory circuit'20148,629,515'Metal gate semiconductor device'20148,624,295'SRAM devices utilizing strained-channel transistors and methods of manufacture'20148,598,630'Photo alignment mark for a gate last process'20138,558,278'Strained transistor with optimized drive current and method of forming'20138,552,522'Dishing-free gap-filling with multiple CMPs'20138,530,326'Method of fabricating a dummy gate structure in a gate last process'20138,502,326'Gate dielectric formation for high-voltage MOS devices'20138,497,169'Method for protecting a gate structure during contact formation'20138,487,382'Device scheme of HKMG gate-last process'20138,476,126'Gate stack for high-K/metal gate last process'20138,461,654'Spacer shape engineering for void-free gap-filling process'20138,461,629'Semiconductor device and method of fabricating same'20138,394,692'Integrating a first contact structure in a gate last process'20138,389,348'Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics'20138,390,072'Chemical mechanical polishing (CMP) method for gate last process'20138,372,706'Semiconductor device fabrication method including hard mask and sacrificial spacer elements'20138,368,170'Reducing device performance drift caused by large spacings between active regions'20138,367,515'Hybrid shallow trench isolation for high-k metal gate device improvement'20138,368,136'Integrating a capacitor in a metal gate last process'20138,361,866'Modifying work function in PMOS devices by counter-doping'20138,349,732'Implanted metal silicide for semiconductor device'20138,349,680'High-k metal gate CMOS patterning method'20138,334,572'Resistive device for high-k metal gate technology'20128,324,046'Poly resistor and poly eFuse design for replacement gate technology'20128,304,839'Poly resistor and poly eFuse design for replacement gate technology'20128,286,114'3-dimensional device design layout'20128,237,227'Dummy gate structure for gate last process'20128,237,201'Layout methods of integrated circuits having unit MOS devices'20128,216,888'Eliminating poly uni-direction line-end shortening using second cut'20128,202,776'Method for protecting a gate structure during contact formation'20128,174,091'Fuse structure'20128,173,491'Standard cell architecture and methods with variable design rules'20128,153,498'Downsize polysilicon height for polysilicon resistor integration of replacement gate process'20128,143,131'Method of fabricating spacers in a strained semiconductor device'20128,138,554'Semiconductor device with local interconnects'20128,125,051'Device layout for gate last process'20128,120,086'Low leakage capacitors including portions in inter-layer dielectrics'20128,115,271'Reducing device performance drift caused by large spacings between active regions'20128,105,891'Method for tuning a work function of high-K metal gate devices'20128,105,929'Gate control and endcap improvement'20128,093,116'Method for N/P patterning in a gate last process'20128,093,120'Integrating a first contact structure in a gate last process'20128,058,119'Device scheme of HKMG gate-last process'20118,048,752'Spacer shape engineering for void-free gap-filling process'20118,039,381'Photoresist etch back method for gate last process'20118,035,165'Integrating a first contact structure in a gate last process'20118,017,473'Modifying work function in PMOS devices by counter-doping'20118,008,145'High-K metal gate structure fabrication method including hard mask'20117,998,830'Semiconductor device with both I/O and core components and method of fabricating same'20117,985,690'Method for a gate last process'20117,981,801'Chemical mechanical polishing (CMP) method for gate last process'20117,977,754'Poly resistor and poly eFuse design for replacement gate technology'20117,977,181'Method for gate height control in a gate last process'20117,977,202'Reducing device performance drift caused by large spacings between active regions'20117,955,964'Dishing-free gap-filling with multiple CMPs'20117,939,392'Method for gate height control in a gate last process'20117,939,384'Eliminating poly uni-direction line-end shortening using second cut'20117,927,943'Method for tuning a work function of high-k metal gate devices'20117,923,321'Method for gap filling in a gate last process'20117,919,792'Standard cell architecture and methods with variable design rules'20117,898,037'Contact scheme for MOSFETs'20117,868,386'Method and apparatus for semiconductor device with improved source/drain junctions'20117,868,361'Semiconductor device with both I/O and core components and method of fabricating same'20117,833,848'Method for removing hard masks on gates in semiconductor manufacturing process'20107,812,379'SOI devices'20107,803,674'Methods for fabricating SOI devices'20107,768,069'FIN-FET device structure'20107,750,416'Modifying work function in PMOS devices by counter-doping'20107,701,034'Dummy patterns in integrated circuit fabrication'20107,678,636'Selective formation of stress memorization layer'20107,632,729'Method for semiconductor device performance enhancement'20097,612,364'MOS devices with source/drain regions having stressed regions and non-stressed regions'20097,550,795'SOI devices and methods for fabricating the same'20097,525,177'Controllable varactor within dummy substrate pattern'20097,470,992'Barrier layer stack to prevent Ti diffusion'20087,432,179'Controlling gate formation by removing dummy gate structures'20087,404,167'Method for improving design window'20087,364,957'Method and apparatus for semiconductor device with improved source/drain junctions'20087,332,756'Damascene gate structure with a resistive device'20087,298,011'Semiconductor device with recessed L-shaped spacer and method of fabricating the same'20077,157,351'Ozone vapor clean method'20077,064,056'Barrier layer stack to prevent Ti diffusion'20067,030,728'Layout and method to improve mixed-mode resistor performance'20067,026,195'Planarizing method for forming FIN-FET device'20066,881,996'Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer'20056,812,088'Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer'20046,732,422'Method of forming resistors'20046,710,413'Salicide field effect transistors with improved borderless contact structures and a method of fabrication'20046,667,217'Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process'20036,472,721'Dual damascene interconnect structures that include radio frequency capacitors and inductors'20026,350,662'Method to reduce defects in shallow trench isolations by post liner anneal'20026,335,249'Salicide field effect transistors with improved borderless contact structures and a method of fabrication'20026,329,234'Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow'20016,265,271'Integration of the borderless contact salicide process'20016,214,698'Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer'20016,110,793'Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits'20006,080,638'Formation of thin spacer at corner of shallow trench isolation (STI)'20006,046,103'Borderless contact process for a salicide devices'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (123)· patent assignee history
2000–2021Based in Hsinchu, TW· patent location history
2011–2016Patents assigned to THEI KONG-BENG (54)· patent assignee history
2011–2015Patents assigned to CHUANG HARRY (40)· patent assignee history
2011–2021Based in Kuei Shan Hsiang, TW· patent location history
2011–2018Based in Hsinchu County, TW· patent location history
2012–2014Patents assigned to LIANG MONG-SONG (13)· patent assignee history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (56)· patent assignee history
2016Based in Shen Zen, TW· patent location history
2020–2021Based in Hinschu Country, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG1232000–2016
TAIWAN SEMICONDUCTOR MFG CO LTD562015–2021
THEI KONG-BENGself542011–2016
CHUANG HARRY402011–2015
LIANG MONG-SONG132012–2014
Locations
LocationPatentsSpan
Hsinchu, TW1052000–2021
Kuei Shan Hsiang, TW502011–2021
Hsinchu County, TW152011–2018
Hinschu Country, TW22020–2021
Shen Zen, TW12016