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Inventor

John A. Wishneusky

Inventor
Fitzwilliam, NH, US

Overview

23→
Patents
1981–2013
Patent span
Physics
Primary field (CPC G)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing61%
H04LTransmission of digital information, e.g. telegraphic communication11%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems7%
G06TImage data processing or generation, in general4%
G11CStatic stores4%
H02JElectric power networks4%
H03KPulse technique4%
H03MCoding4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
8,452,897'Method for using a multi-master multi-slave bus for power management'20138,239,597'Device-to-device communication bus for distributed power management'20127,908,402'Integrated multi-function point-of-load regulator circuit'20117,793,005'Power management system using a multi-master multi-slave bus and multi-function point-of-load regulators'20107,685,320'Autonomous sequencing and fault spreading'20107,653,757'Method for using a multi-master multi-slave bus for power management'20107,522,620'Method and apparatus for scheduling packets'20097,426,215'Method and apparatus for scheduling packets'20087,415,027'Processing frame bits'20087,243,214'Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary'20077,007,156'Multiple coprocessor architecture to process a plurality of subtasks in parallel'20066,981,113'Storage registers for a processor pipeline'20056,963,535'MAC bus interface'20056,901,507'Context scheduling'20056,874,080'Context processing by substantially simultaneously selecting address and instruction of different contexts'20056,826,676'Extending immediate operands across plural computer instructions with indication of how many instructions are used to store the immediate operand'20045,864,716'Tagged data compression for parallel port interface'19995,781,799'DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers'19985,765,023'DMA controller having multiple channels and buffer pool having plurality of buffers accessible to each channel for buffering data transferred to and from host computer'19985,588,145'Method and arrangement for clock adjustment using programmable period binary rate multiplier'19965,566,352'Register-read acknowledgment and prioritization for integration with a hardware-based interrupt acknowledgment mechanism'19964,975,828'Multi-channel data communications controller'19904,254,477'Reconfigurable memory circuit'1981

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–1999Patents assigned to CIRRUS LOGIC INC (6)· patent assignee history
1990Based in Sunnyvale, CA, US· patent location history
1996–1999Based in Bolton, MA, US· patent location history
1998Based in Boston, MA, US· patent location history
2004–2009Patents assigned to INTEL CORP (10)· patent assignee history
2004–2009Based in Fitzwilliam, NH, US· patent location history
2010–2013Patents assigned to ZILKER LABS INC (5)· patent assignee history
2010–2013Based in Austin, TX, US· patent location history
2012–2013Patents assigned to WISHNEUSKY JOHN A (2)· patent assignee history
2013Patents assigned to FERNALD KENNETH W (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP102004–2009
CIRRUS LOGIC INC61990–1999
ZILKER LABS INC52010–2013
WISHNEUSKY JOHN Aself22012–2013
FERNALD KENNETH W12013
Locations
LocationPatentsSpan
Fitzwilliam, NH, US102004–2009
Austin, Texas, US62010–2013
Bolton, Massachusetts, US41996–1999
Boston, Massachusetts, US11998
Sunnyvale, California, US11990