Inventor
Steven J. Koester
Inventor
Ossining, NY, US
Overview
Patents· 74 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10BElectronic memory devices7%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation7%
F01DNon-positive displacement machines or engines, e.g. steam turbines5%
F05DIndexing scheme for aspects relating to non-positive-displacement machines or engines, gas-turbines or jet-propulsion plants5%
H01LSemiconductor devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
B82YSpecific uses or applications of nanostructures2%
PatentTitleYear
11,111,795Turbine rotor airfoil and corresponding method for reducing pressure loss in a cavity within a blade202111,085,306Turbine rotor blade with airfoil cooling integrated with impingement platform cooling202111,079,371Chemical sensors with non-covalent surface modification of graphene202110,712,302Ultra-compact, passive, varactor-based wireless sensor using quantum capacitance effect in graphene202010,526,900Shrouded turbine blade202010,196,906Turbine blade with a non-constraint flow turning guide structure201910,191,005Ultra-compact, passive, varactor-based wireless sensor using quantum capacitance effect in graphene201910,060,270Internal cooling system with converging-diverging exit slots in trailing edge cooling channel for an airfoil in a turbine engine20189,805,949'High κ gate stack on III-V compound semiconductors'20179,745,853'Integrated circuit cooled turbine blade'20179,631,506'Turbine abradable layer with composite non-inflected bi-angle ridges and grooves'20179,513,244'Ultra-compact, passive, varactor-based wireless sensor using quantum capacitance effect in graphene'20169,494,043'Turbine blade having contoured tip shroud'20169,178,061'Method for fabricating MOSFET on silicon-on-insulator with internal body contact'20158,969,992'Autonomous integrated circuits'20158,962,448'Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier'20158,796,735'Fabrication of a vertical heterojunction tunnel-FET'20148,766,410'Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors'20148,738,167'3D integrated circuit device fabrication with precisely controllable substrate removal'20148,722,492'Nanowire pin tunnel field effect devices'20148,716,810'Selective floating body SRAM cell'20148,674,515'3D integrated circuits structure'20148,664,081'Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier'20148,629,553'3D integrated circuit device fabrication with precisely controllable substrate removal'20148,587,121'Backside dummy plugs for 3D integration'20138,492,869'3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer'20138,431,476'Method to prevent surface decomposition of III-V compound semiconductors'20138,432,723'Nano-electro-mechanical DRAM cell'20138,426,921'Three-dimensional integrated circuits and techniques for fabrication thereof'20138,415,772'Method to prevent surface decomposition of III-V compound semiconductors'20138,399,336'Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer'20138,378,429'Selective floating body SRAM cell'20138,349,670'Selective floating body SRAM cell'20138,343,838'Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor by implanting blocking impurity into the strained-layer'20138,298,914'3D integrated circuit device fabrication using interface wafer as permanent carrier'20128,273,649'Method to prevent surface decomposition of III-V compound semiconductors'20128,263,477'Structure for use in fabrication of PiN heterojunction TFET'20128,258,031'Fabrication of a vertical heterojunction tunnel-FET'20128,247,904'Interconnection between sublithographic-pitched structures and lithographic-pitched structures'20128,212,218'Dosimeter powered by passive RF absorption'20128,158,515'Method of making 3D integrated circuits'20128,129,811'Techniques for three-dimensional circuit integration'20128,129,256'3D integrated circuit device fabrication with precisely controllable substrate removal'20128,080,805'FET radiation monitor'20118,018,007'Selective floating body SRAM cell'20117,989,900'Semiconductor structure including gate electrode having laterally variable work function'20117,985,633'Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors'20117,964,896'Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics'20117,955,887'Techniques for three-dimensional circuit integration'20117,915,653'Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector'20117,897,428'Three-dimensional integrated circuits and techniques for fabrication thereof'20117,871,869'Extremely-thin silicon-on-insulator transistor with raised source/drain'20117,781,288'Semiconductor structure including gate electrode having laterally variable work function'20107,652,332'Extremely-thin silicon-on-insulator transistor with raised source/drain'20107,521,376'Method of forming a semiconductor structure using a non-oxygen chalcogen passivation treatment'20097,510,904'Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector'20097,504,311'Structure and method of integrating compound and elemental semiconductors for high-performance CMOS'20097,393,735'Structure for and method of fabricating a high-mobility field-effect transistor'20087,282,425'Structure and method of integrating compound and elemental semiconductors for high-performance CMOS'20077,183,175'Shallow trench isolation structure for strained Si on SiGe'20077,138,697'Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector'20067,083,998'Si/SiGe optoelectronic integrated circuits'20067,084,431'High speed composite p-channel Si/SiGe heterostructure for field effect devices'20067,074,686'Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications'20066,972,440'Enhanced T-gate structure for modulation doped field effect transistors'20056,972,250'Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device'20056,949,761'Structure for and method of fabricating a high-mobility field-effect transistor'20056,858,502'High speed composite p-channel Si/SiGe heterostructure for field effect devices'20056,805,962'Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications'20046,784,466'Si/SiGe optoelectronic integrated circuits'20046,743,651'Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen'20046,740,535'Enhanced T-gate structure for modulation doped field effect transistors'20046,690,072'Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device'20046,350,993'High speed composite p-channel Si/SiGe heterostructure for field effect devices'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2015Patents assigned to IBM (60)· patent assignee history
2002–2017Based in Ossining, NY, US· patent location history
2012–2017Patents assigned to KOESTER STEVEN J (26)· patent assignee history
2012–2015Patents assigned to FAROOQ MUKTA G (10)· patent assignee history
2012–2015Patents assigned to IYER SUBRAMANIAN S (10)· patent assignee history
2012–2015Patents assigned to HANNON ROBERT (8)· patent assignee history
2012–2014Based in Yorktown Heights, NY, US· patent location history
2015–2021Based in Edina, MN, US· patent location history
2016–2017Based in Sharonville, OH, US· patent location history
2018–2021Based in Toledo, OH, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 60 | 2002–2015 |
| KOESTER STEVEN Jself | 26 | 2012–2017 |
| FAROOQ MUKTA G | 10 | 2012–2015 |
| IYER SUBRAMANIAN S | 10 | 2012–2015 |
| HANNON ROBERT | 8 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ossining, New York, US | 54 | 2002–2017 |
| Toledo, OH, US | 5 | 2018–2021 |
| Edina, Minnesota, US | 5 | 2015–2021 |
| Yorktown Heights, New York, US | 4 | 2012–2014 |
| Sharonville, OH, US | 3 | 2016–2017 |