Inventor
Krishna Seshan
Inventor
San Jose, CA, US
Overview
Patents· 55 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1042%
H10DInorganic electric semiconductor devices9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
G01RMeasuring electric variables5%
G06FElectric digital data processing4%
H05KPrinted circuits4%
Y02PClimate change mitigation technologies in the production or processing of goods4%
Y10TTechnical subjects covered by former us classification4%
B23KSoldering or unsoldering2%
PatentTitleYear
7,960,831'Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same'20117,511,370'Power gridding scheme'20097,425,458'Selectable decoupling capacitors for integrated circuits and associated methods'20087,411,269'Isolation structure configurations for modifying stresses in semiconductor devices'20087,410,858'Isolation structure configurations for modifying stresses in semiconductor devices'20087,314,819'Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same'20087,262,070'Method to make a weight compensating/tuning layer on a substrate'20077,250,333'Method of fabricating a linearized output driver and terminator'20077,202,568'Semiconductor passivation deposition process for interfacial adhesion'20077,056,817'Forming a cap above a metal layer'20067,034,402'Device with segmented ball limiting metallurgy'20067,033,923'Method of forming segmented ball limiting metallurgy'20067,012,304'Diode and transistor design for high speed I/O'20066,979,896'Power gridding scheme'20056,937,458'Selectable decoupling capacitors for integrated circuit and methods of use'20056,930,379'Power gridding scheme'20056,914,658'Method for fabricating a moat around an active pixel area of a microelectronic image projection device'20056,876,053'Isolation structure configurations for modifying stresses in semiconductor devices'20056,734,544'Integrated circuit package'20046,715,663'Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method'20046,686,659'Selectable decoupling capacitors for integrated circuit and methods of use'20046,646,324'Method and apparatus for a linearized output driver and terminator'20036,614,118'Structures to mechanically stabilize isolated top-level metal lines'20036,577,502'Mobile computer having a housing with openings for cooling'20036,552,425'Integrated circuit package'20036,521,996'Ball limiting metallurgy for input/outputs and methods of fabrication'20036,515,358'Integrated passivation process, probe geometry and probing process'20036,480,385'Electronic assembly and cooling thereof'20026,480,059'Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances'20026,459,573'Mobile computer having a housing with openings for cooling'20026,376,899'Planar guard ring'20026,377,457'Electronic assembly and cooling thereof'20026,357,330'Method and apparatus for cutting a wafer'20026,352,940'Semiconductor passivation deposition process for interfacial adhesion'20026,162,652'Process for sort testing C4 bumped wafers'20006,163,065'Energy-absorbing stable guard ring'20006,143,668'KLXX technology with integrated passivation process, probe geometry and probing process'20006,137,143'Diode and transistor design for high speed I/O'20006,137,155'Planar guard ring'20006,100,709'Silicon wafer testing rig and a method for testing a silicon wafer wherein the silicon wafer is bent into a dome shape'20006,090,650'Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances'20006,046,101'Passivation technology combining improved adhesion in passivation and a scribe street without passivation'20006,043,551'Metal locking structures to prevent a passivation layer from delaminating'20005,977,639'Metal staples to prevent interlayer delamination'19995,880,528'Energy absorbing structures to prevent damage to an integrated circuit'19995,622,892'Method of making a self cooling electrically programmable fuse'19975,614,440'Method of forming a thermally activated noise immune fuse'19975,585,663'Self cooling electrically programmable fuse'19965,504,434'Instrument for the measurement of electrical characteristics during manufacturing processes'19965,444,287'Thermally activated noise immune fuse'19955,298,784'Electrically programmable antifuse using metal penetration of a junction'19945,213,249'Ultrasonic adhesion/dehesion monitoring apparatus with power feedback measuring means'19935,170,929'Ultrasonic adhesion/dehesion monitoring apparatus with acoustic transducer means'19925,154,514'On-chip temperature sensor utilizing a Schottky barrier diode structure'19924,962,294'Method and apparatus for causing an open circuit in a conductive line'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–1997Patents assigned to IBM (10)· patent assignee history
1990–1996Based in Beacon, NY, US· patent location history
1995–2011Based in San Jose, CA, US· patent location history
1999–2011Patents assigned to INTEL CORP (45)· patent assignee history
2007Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 45 | 1999–2011 |
| IBM | 10 | 1990–1997 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 48 | 1995–2011 |
| Beacon, New York, US | 6 | 1990–1996 |
| Santa Clara, California, US | 1 | 2007 |