Inventor
Randhir P. S. Thakur
Inventor
Boise, ID, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10BElectronic memory devices19%
H10DInorganic electric semiconductor devices16%
G11CStatic stores14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
Y10TTechnical subjects covered by former us classification5%
C30BSingle-crystal growth2%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light2%
G01KMeasuring temperature2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
7,618,901'Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3'20097,235,498'Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3 '20077,232,728'High quality oxide on an epitaxial layer'20076,864,125'Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3 '20056,703,690'Apparatus for reducing isolation stress in integrated circuits'20046,607,946'Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3'20036,602,798'Method and apparatus for reducing isolation stress in integrated circuits'20036,476,433'Semiconductor interconnection structure and method'20026,414,376'Method and apparatus for reducing isolation stress in integrated circuits'20026,414,364'Isolation structure and process therefor'20026,404,669'Reduced leakage DRAM storage unit'20026,265,282'Process for making an isolation structure'20016,181,594'Reduced leakage DRAM storage unit'20016,172,387'Semiconductor interconnection structure and method'20016,157,565'Reduced leakage DRAM storage unit'20006,157,566'Reduced leakage DRAM storage unit'20006,051,511'Method and apparatus for reducing isolation stress in integrated circuits'20006,005,801'Reduced leakage DRAM storage unit'19995,973,954'Reduced leakage DRAM storage unit'19995,926,742'Controlling semiconductor structural warpage in rapid thermal processing by selective and dynamic control of a heating source'1999RE036050'Method for repeatable temperature measurement using surface reflectivity'19995,851,929'Controlling semiconductor structural warpage in rapid thermal processing by selective and dynamic control of a heating source'19985,738,909'Method of forming high-integrity ultrathin oxides'19985,416,045'Method for chemical vapor depositing a titanium nitride layer on a semiconductor wafer and method of annealing tin films'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2009Patents assigned to MICRON TECHNOLOGY INC (24)· patent assignee history
1995–2009Based in Boise, ID, US· patent location history
2001–2002Based in Cupertino, CA, US· patent location history
2001–2002Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 24 | 1995–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 20 | 1995–2009 |
| Cupertino, California, US | 2 | 2001–2002 |
| San Jose, California, US | 2 | 2001–2002 |