Inventor
William Michael Lye
Inventor
Coquitlam, CA
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Mprimary
H03MCoding23%
H03KPulse technique19%
H04LTransmission of digital information, e.g. telegraphic communication19%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses14%
H03FAmplifiers7%
H04BTransmission7%
H10DInorganic electric semiconductor devices5%
G01RMeasuring electric variables2%
G04FTime-interval measuring2%
G06FElectric digital data processing2%
PatentTitleYear
10,587,281Radio frequency flash ADC circuits202010,326,468Digital-to-analog converter system and method201910,141,945Radio frequency flash ADC circuits20189,906,236'Digital-to-analog converter system and method'20189,847,788Radio frequency flash ADC circuits20179,413,394'Digital to-analog converter system and method'20169,231,600'Low-noise flexible frequency clock generation from two fixed-frequency references'20169,225,507'System and method for synchronizing local oscillators'20159,225,508'Low-noise flexible frequency clock generation from two fixed-frequency references'20159,215,062'Low-noise flexible frequency clock generation from two fixed-frequency references'20159,124,287'Scrambler with built in test capabilities for unary DAC'20159,112,517'Low-noise flexible frequency clock generation from two fixed-frequency references'20159,094,033'Quantization noise-shaping device'20158,773,296'Interleaved digital to analog conversion'20148,467,436'DSP-based diagnostics for monitoring a SerDes link'20137,986,190'Jitter attenuation with a fractional-N clock synthesizer'20117,985,644'Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region'20117,646,063'Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions'20107,501,851'Configurable voltage mode transmitted architecture with common-mode adjustment and novel pre-emphasis'20097,288,971'Systems and methods for actively-peaked current-mode logic'20077,205,820'Systems and methods for translation of signal levels across voltage domains'20077,202,706'Systems and methods for actively-peaked current-mode logic'20077,023,941'Joint equalization and timing acquisition for RZ signals'20066,408,032'Transmit baseline wander correction technique'20026,054,884'Process-insensitive controllable CMOS delay line'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2002Patents assigned to PMC SIERRA LTD (2)· patent assignee history
2000–2002Based in Burnaby, CA· patent location history
2006–2011Patents assigned to PMC SIERRA INC (8)· patent assignee history
2006–2020Based in Coquitlam, CA· patent location history
2013–2016Patents assigned to PMC SIERRA US INC (9)· patent assignee history
2013Patents assigned to BOYD GRAEME B (1)· patent assignee history
2017–2020Patents assigned to Maxlinear Asia Singapore PTE LTD (5)· patent assignee history
2019Based in Singapore, SG· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| PMC SIERRA US INC | 9 | 2013–2016 |
| PMC SIERRA INC | 8 | 2006–2011 |
| Maxlinear Asia Singapore PTE LTD | 5 | 2017–2020 |
| PMC SIERRA LTD | 2 | 2000–2002 |
| BOYD GRAEME B | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Coquitlam, CA | 22 | 2006–2020 |
| Burnaby, CA | 2 | 2000–2002 |
| Singapore, SG | 1 | 2019 |