Inventor
Brian J. Greene
Inventor
Wappingers Falls, NY, US
Overview
Patents· 92 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices44%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
G01RMeasuring electric variables1%
G07FCoin-freed or like apparatus1%
G11CStatic stores1%
H10BElectronic memory devices1%
PatentTitleYear
10,984,635Progressive jackpot for deals of instant game ticket where winning progressive jackpot instant ticket is randomly selected from unplayed tickets after coin-in or progressive jackpot amount for the deals of instant tickets reaches predetermined value202110,867,912Dummy fill scheme for use with passive devices202010,796,973Test structures connected with the lowest metallization levels in an interconnect structure202010,790,204Test structure leveraging the lowest metallization level of an interconnect structure202010,672,907Channel region dopant control in fin field effect transistor202010,566,411On-chip resistors with direct wiring connections202010,269,932Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices201910,170,337Implant after through-silicon via (TSV) etch to getter mobile ions201910,083,878Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile201810,074,571Device with decreased pitch contact to active regions20189,991,167Method and IC structure for increasing pitch between gates20189,960,168Capacitor strap connection structure and fabrication method20189,780,002'Threshold voltage and well implantation method for semiconductor devices'20179,673,197'FinFET with constrained source-drain epitaxial region'20179,536,985'Epitaxial growth of material on source/drain regions of FinFET structure'20179,536,879'FinFET with constrained source-drain epitaxial region'20179,443,854'FinFET with constrained source-drain epitaxial region'20169,437,496'Merged source drain epitaxy'20169,379,185'Method of forming channel region dopant control in fin field effect transistor'20169,349,609'Semiconductor process temperature optimization'20169,337,338'Tucked active region without dummy poly for performance boost and variation reduction'20169,312,274'Merged fin structures for finFET devices'20169,305,999'Stress-generating structure for semiconductor-on-insulator devices'20169,299,780'Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device'20169,252,215'Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device'20169,171,954'FinFET structure and method to adjust threshold voltage in a FinFET structure'20159,105,722'Tucked active region without dummy poly for performance boost and variation reduction'20159,093,275'Multi-height multi-composition semiconductor fins'20159,082,877'Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor'20158,993,389'Dummy gate interconnect for semiconductor device'20158,941,189'Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of forming'20158,932,949'FinFET structure and method to adjust threshold voltage in a FinFET structure'20158,927,427'Anticipatory implant for TSV'20158,853,035'Tucked active region without dummy poly for performance boost and variation reduction'20148,835,234'MOS having a sic/sige alloy stack'20148,803,243'Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor'20148,796,771'Creating anisotropically diffused junctions in field effect transistor devices'20148,785,291'Post-gate shallow trench isolation structure formation'20148,779,469'Post-gate shallow trench isolation structure formation'20148,772,149'FinFET structure and method to adjust threshold voltage in a FinFET structure'20148,633,096'Creating anisotropically diffused junctions in field effect transistor devices'20148,629,501'Stress-generating structure for semiconductor-on-insulator devices'20148,598,009'Self-aligned embedded SiGe structure and method of manufacturing the same'20138,513,085'Structure and method to improve threshold voltage of MOSFETs including a high k dielectric'20138,476,706'CMOS having a SiC/SiGe alloy stack'20138,466,496'Selective partial gate stack for improved device isolation'20138,420,468'Strain-compensated field effect transistor and associated method of forming the transistor'20138,354,309'Method of providing threshold voltage adjustment through gate dielectric stack modification'20138,236,661'Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage'20128,222,673'Self-aligned embedded SiGe structure and method of manufacturing the same'20128,217,470'Field effect device including recessed and aligned germanium containing channel'20128,173,531'Structure and method to improve threshold voltage of MOSFETS including a high K dielectric'20128,115,254'Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same'20128,106,455'Threshold voltage adjustment through gate dielectric stack modification'20128,039,331'Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors'20118,030,687'Field effect transistor incorporating at least one structure for imparting temperature-dependent strain on the channel region and associated method of forming the transistor'20117,989,298'Transistor having V-shaped embedded stressor'20117,977,185'Method and apparatus for post silicide spacer removal'20117,943,467'Structure and method to fabricate MOSFET with short gate'20117,939,413'Embedded stressor structure and process'20117,928,436'Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods'20117,883,948'Method and structure for reducing induced mechanical stresses'20117,842,940'Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost'20107,843,024'Method and structure for improving device performance variation in dual stress liner technology'20107,833,873'Method and structure to reduce contact resistance on thin silicon-on-insulator device'20107,812,397'Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof'20107,790,553'Methods for forming high performance gates and structures thereof'20107,767,541'Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods'20107,759,739'Transistor with dielectric stressor elements'20107,687,865'Method and structure to reduce contact resistance on thin silicon-on-insulator device'20107,659,581'Transistor with dielectric stressor element fully underlying the active semiconductor region'20107,659,157'Dual metal gate finFETs with single or dual high-K gate dielectric'20107,572,689'Method and structure for reducing induced mechanical stresses'20097,542,330'SRAM with asymmetrical pass gates'20097,538,339'Scalable strained FET device and method of fabricating the same'20097,534,667'Structure and method for fabrication of deep junction silicon-on-insulator transistors'20097,507,631'Epitaxial filled deep trench structures'20097,501,651'Test structure of semiconductor device'20097,479,437'Method to reduce contact resistance on thin silicon-on-insulator device'20097,476,938'Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress'20097,462,522'Method and structure for improving device performance variation in dual stress liner technology'20087,449,374'Methods of manufacturing semiconductor devices with rotated substrates'20087,449,378'Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions'20087,442,618'Method to engineer etch profiles in Si substrate for advanced semiconductor devices'20087,410,852'Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors'20087,405,131'Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor'20087,365,399'Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost'20087,358,551'Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions'20087,317,204'Test structure of semiconductor device'20087,205,639'Semiconductor devices with rotated substrates and methods of manufacture thereof'20077,132,322'Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device'20067,002,209'MOSFET structure with high mechanical stress in the channel'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2020Patents assigned to IBM (76)· patent assignee history
2006–2013Based in Yorktown Heights, NY, US· patent location history
2006–2011Based in Danbury, CT, US· patent location history
2009–2020Based in Wappingers Falls, NY, US· patent location history
2012–2020Patents assigned to GLOBALFOUNDRIES INC (18)· patent assignee history
2012–2014Patents assigned to GREENE BRIAN J (18)· patent assignee history
2012–2014Patents assigned to LIANG YUE (7)· patent assignee history
2012–2014Patents assigned to YU XIAOJUN (7)· patent assignee history
2015–2019Based in Fishkill, NY, US· patent location history
2019–2020Based in Saratoga Springs, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 76 | 2006–2020 |
| GLOBALFOUNDRIES INC | 18 | 2012–2020 |
| GREENE BRIAN Jself | 18 | 2012–2014 |
| LIANG YUE | 7 | 2012–2014 |
| YU XIAOJUN | 7 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 42 | 2009–2020 |
| Yorktown Heights, New York, US | 24 | 2006–2013 |
| Fishkill, New York, US | 9 | 2015–2019 |
| Danbury, CT, US | 8 | 2006–2011 |
| Saratoga Springs, New York, US | 3 | 2019–2020 |