LexDanaLexDanabeta
Inventor

Yao-Sheng Lee

Inventor
Tampa, FL, US

Overview

64→
Patents
2012–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices28%
H01LSemiconductor devices25%
H10DInorganic electric semiconductor devices24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
G11CStatic stores3%
H10NElectric solid-state devices not otherwise provided for2%
A63FCard, board, or roulette games0%
B42DBooks0%
PatentTitleYear
10,847,408Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip202010,741,572Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and method of making the same202010,700,086Three-dimensional flat NAND memory device having high mobility channels and methods of making the same202010,622,368Three-dimensional memory device with semicircular metal-semiconductor alloy floating gate electrodes and methods of making thereof202010,475,879Support pillar structures for leakage reduction in a three-dimensional memory device and methods of making the same201910,468,596Damascene process for forming three-dimensional cross rail phase change memory devices201910,461,163Three-dimensional memory device with thickened word lines in terrace region and method of making thereof201910,438,964Three-dimensional memory device having direct source contact and metal oxide blocking dielectric and method of making thereof201910,381,434Support pillar structures for leakage reduction in a three-dimensional memory device201910,269,620Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof201910,262,945Three-dimensional array device having a metal containing barrier and method of making thereof201910,256,247Three-dimensional memory device with silicided word lines, air gap layers and discrete charge storage elements, and method of making thereof201910,199,434Three-dimensional cross rail phase change memory device and method of manufacturing the same201910,128,261Cobalt-containing conductive layers for control gate electrodes in a memory structure201810,056,399Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same201810,014,316Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof20189,893,081'Ridged word lines for increasing control gate lengths in a three-dimensional memory device'20189,887,207'Three dimensional NAND device having dummy memory holes and method of making thereof'20189,824,966'Three-dimensional memory device containing a lateral source contact and method of making the same'20179,793,139'Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines'20179,780,182'Molybdenum-containing conductive layers for control gate electrodes in a memory structure'20179,691,884'Monolithic three dimensional NAND strings and methods of fabrication thereof'20179,679,906'Three-dimensional memory devices containing memory block bridges'20179,672,917'Stacked vertical memory array architectures, systems and methods'20179,646,990'NAND memory strings and methods of fabrication thereof'20179,627,399'Three-dimensional memory device with metal and silicide control gates'20179,627,403'Multilevel memory stack structure employing support pillar structures'20179,570,460'Spacer passivation for high-aspect ratio opening film removal and cleaning'20179,570,463'Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same'20179,570,455'Metal word lines for three dimensional memory devices'20179,553,146'Three dimensional NAND device having a wavy charge storage layer'20179,530,791'Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same'20169,524,779'Three dimensional vertical NAND device with floating gates'20169,520,406'Method of making a vertical NAND device using sequential etching of multilayer stacks'20169,515,079'Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack'20169,496,274'Three-dimensional non-volatile memory device'20169,478,558'Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer'20169,460,931'High aspect ratio memory hole channel contact formation'20169,449,982'Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks'20169,437,606'Method of making a three-dimensional memory array with etch stop'20169,431,409'Method of making a three-dimensional memory array with etch stop'20169,397,107'Methods of making three dimensional NAND devices'20169,379,132'NAND memory strings and methods of fabrication thereof'20169,356,031'Three dimensional NAND string memory devices with voids enclosed between control gate electrodes'20169,305,935'Multi-level contact to a 3D memory array and method of making'20169,305,932'Methods of making three dimensional NAND devices'20169,227,456'Memories with cylindrical read/write stacks'20169,230,973'Methods of fabricating a three-dimensional non-volatile memory device'20169,159,739'Floating gate ultrahigh density vertical NAND flash memory'20159,099,496'Method of forming an active area with floating gate negative offset profile in FG NAND memory'20159,093,321'Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device'20159,093,480'Spacer passivation for high aspect ratio etching of multilayer stacks for three dimensional NAND device'20159,023,719'High aspect ratio memory hole channel contact formation'20158,994,099'Multi-level contact to a 3D memory array and method of making'20158,987,089'Methods of fabricating a three-dimensional non-volatile memory device'20158,946,023'Method of making a vertical NAND device using sequential etching of multilayer stacks'20158,933,501'Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device'20158,828,884'Multi-level contact to a 3D memory array and method of making'20148,658,499'Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device'20148,614,126'Method of making a three-dimensional memory array with etch stop'20138,461,641'Ultrahigh density vertical NAND memory device and method of making thereof'20138,330,208'Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof'20128,252,192'Method of pattern etching a dielectric film while removing a mask layer'20128,187,936'Ultrahigh density vertical NAND memory device and method of making thereof'2012

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2012–2018Patents assigned to SANDISK TECHNOLOGIES INC (41)· patent assignee history
2012–2016Patents assigned to LEE YAO-SHENG (7)· patent assignee history
2012–2016Patents assigned to ALSMEIER JOHANN (5)· patent assignee history
2012Patents assigned to CHIEN HENRY (2)· patent assignee history
2012–2020Based in Tampa, FL, US· patent location history
2016–2020Patents assigned to SANDISK TECHNOLOGIES LLC (41)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK TECHNOLOGIES INC412012–2018
SANDISK TECHNOLOGIES LLC412016–2020
LEE YAO-SHENGself72012–2016
ALSMEIER JOHANN52012–2016
CHIEN HENRY22012
Locations
LocationPatentsSpan
Tampa, Florida, US642012–2020