LexDanaLexDanabeta
Inventor

Akira Umezawa

Inventor
Tokyo, JP

Overview

52→
Patents
1996–2020
Patent span
Physics
Primary field (CPC G)

Patents· 52 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores60%
H10BElectronic memory devices19%
H10DInorganic electric semiconductor devices6%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems4%
G06KGraphical data reading2%
F16LPipes1%
G01KMeasuring temperature1%
H01LSemiconductor devices1%
H03FAmplifiers1%
H03KPulse technique1%
PatentTitleYear
10,811,393Memory device20208,432,744'Semiconductor storage device with a well control circuit'20138,331,156'Nonvolatile semiconductor storage device with multiple well regions and a shared bit line'20128,259,493'Nonvolatile semiconductor storage device and method of testing the same'20128,169,253'Power circuit including step-up circuit and stabilizing method thereof'20128,094,496'Nonvolatile semiconductor memory device and control method thereof'20127,672,164'Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate'20107,577,032'Non-volatile semiconductor memory device'20097,505,355'Semiconductor memory device with MOS transistors each having floating gate and control gate'20097,505,327'Method of controlling a semiconductor device by a comparison of times for discharge of bit lines connected to different memory cell arrays'20097,505,324'Semiconductor memory device with a stacked gate including a floating gate and a control gate'20097,480,180'Semiconductor memory device comprising plural source lines'20097,466,610'Non-volatile semiconductor memory device'20087,447,063'Nonvolatile semiconductor memory device'20087,423,910'Semiconductor device including MOS transistors having floating gate and control gate'20087,376,023'Semiconductor memory device with MOS transistors each having floating gate and control gate and method of controlling the same'20087,332,766'Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate'20087,312,503'Semiconductor memory device including MOS transistors each having a floating gate and a control gate'20077,280,407'Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same'20077,263,003'Two-transistor flash memory device using replica cell array to control the precharge/discharge and sense amplifier circuits of the primary cell array'20077,245,530'Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same'20077,233,513'Semiconductor memory device with MOS transistors each having floating gate and control gate'20077,233,526'Semiconductor memory device with MOS transistors each having floating gate and control gate'20077,212,434'Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, and a memory card including the same'20077,180,789'Semiconductor memory device with MOS transistors, each having a floating gate and a control gate, and memory card including the same'20077,120,057'Semiconductor memory device with a stacked gate including a floating gate and a control gate'20067,120,053'Semiconductor intergrated circuit device with a main cell array and a fuse cell array whose word lines and bit lines are extended in the same directions'20067,099,191'Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device'20066,961,268'Nonvolatile semiconductor memory device with MOS transistors each having a floating gate and a control gate'20056,943,402'Nonvolatile semiconductor memory device including MOS transistors each having a floating gate and control gate'20056,940,762'Semiconductor memory device including MOS transistor having a floating gate and a control gate'20056,940,754'Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device'20056,856,543'Semiconductor integrated circuit device with erasable and programmable fuse memory'20056,816,421'Nonvolatile semiconductor memory'20046,795,352'Nonvolatile semiconductor memory having page mode with a plurality of banks'20046,700,817'Semiconductor integrated circuit device with operation/function setting information memory'20046,671,203'Nonvolatile semiconductor memory having page mode with a plurality of banks'20036,480,426'Semiconductor integrated circuit device'20026,333,662'Latch type level shift circuit'20016,320,428'Semiconductor integrated circuit device'20016,256,227'Non-volatile semiconductor memory having column sub-selector layout pattern adaptable to miniaturization of memory cell'20016,226,224'Semiconductor integrated circuit device and storage device'20016,222,774'Data-erasable non-volatile semiconductor memory device'20016,195,307'Booster circuit and semiconductor memory device having the same'20016,111,456'Semiconductor circuit'20006,108,246'Semiconductor memory device'20006,052,313'Semiconductor integrated circuit device'20006,041,012'Semiconductor integrated circuit device having a booster circuit and a storage device'20006,041,011'Booster circuit and semiconductor memory device having the same'20006,034,567'Semiconductor integrated circuit device provided with a differential amplifier'20005,909,406'Semiconductor memory device'19995,568,419'Non-volatile semiconductor memory device and data erasing method therefor'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2013Patents assigned to TOSHIBA KK (50)· patent assignee history
1996–2007Based in Yokohama, JP· patent location history
2000Based in Kanagawa, JP· patent location history
2004–2020Based in Tokyo, JP· patent location history
2008Based in Shinagawa-ku, JP· patent location history
2012–2013Patents assigned to UMEZAWA AKIRA (5)· patent assignee history
2012Patents assigned to CHIN GYOSHO (1)· patent assignee history
2012Patents assigned to HIRATA YOSHIHARU (1)· patent assignee history
2013Patents assigned to ARIZONO DAISUKE (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TOSHIBA KK501996–2013
UMEZAWA AKIRAself52012–2013
ARIZONO DAISUKE12013
CHIN GYOSHO12012
HIRATA YOSHIHARU12012
Locations
LocationPatentsSpan
Tokyo, JP282004–2020
Yokohama, JP221996–2007
Shinagawa-ku, JP12008
Kanagawa, JP12000