Inventor
YI-KAN CHENG
Inventor
TW
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices22%
G06FElectric digital data processing21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
H10DInorganic electric semiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
Y02PClimate change mitigation technologies in the production or processing of goods4%
B82YSpecific uses or applications of nanostructures1%
G01RMeasuring electric variables1%
G11CStatic stores1%
H01FMagnets1%
PatentTitleYear
12,588,278Semiconductor device having different size active regions and method of making202612,578,386Scan chain control202612,532,731Interconnect structure202612,462,086Integrated circuit having hybrid sheet structure202512,424,515SOIC chip architecture202512,277,379Method and system for generating layout diagram including wiring arrangement202512,261,116Backside signal routing202512,230,624Integrated circuit with mixed row heights202512,223,252Through-silicon via in integrated circuit packaging202512,216,981System and method for generating layout diagram including wiring arrangement202512,106,030Method of forming merged pillar structures and method of generating layout diagram of same202412,009,260Method and system of forming integrated circuit202412,002,776Interconnect structure and method for forming the same202411,983,475Method for manufacturing a cell having pins and semiconductor device based on same202411,923,302Semiconductor device and method of manufacture202411,893,333Hybrid sheet layout, method, system, and structure202411,790,151System for generating layout diagram including wiring arrangement202311,775,727Method for generating layout diagram including wiring arrangement202311,769,766Integrated circuit with mixed row heights202311,704,472Standard cells and variations thereof within a standard cell library202311,694,973Electromagnetic shielding metal-insulator-metal capacitor structure202311,586,797Through-silicon vias in integrated circuit packaging202311,574,107Method for manufacturing a cell having pins and semiconductor device based on same202311,545,298Method of forming entangled inductor structures202311,532,580Interconnect structure, semiconductor structure including interconnect structure and method for forming the same202211,532,613Structure and method for cooling three-dimensional integrated circuits202211,410,929Semiconductor device and method of manufacture202211,387,177Package structure and method for forming the same202211,367,695Interposer with capacitors202211,282,829Integrated circuit with mixed row heights202211,182,533Standard cells and variations thereof within a standard cell library202111,157,677Merged pillar structures and method of generating layout diagram of same202111,138,360Semiconductor device with filler cell region, method of generating layout diagram and system for same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (33)· patent assignee history
2021–2026Based in TW· patent location history
2023Patents assigned to TAIWAN SEMICONDUCTOR MANUFACUTRING CO LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 33 | 2021–2026 |
| TAIWAN SEMICONDUCTOR MANUFACUTRING CO LTD | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 33 | 2021–2026 |