Inventor
Leah M. Miller
Inventor
Fremont, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1040%
H05KPrinted circuits28%
Y10TTechnical subjects covered by former us classification10%
C03CChemical composition of glasses, glazes or vitreous enamels5%
G01RMeasuring electric variables5%
B65GTransport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors3%
C23CCoating metallic material3%
G06FElectric digital data processing3%
H01RElectrically-conductive connections3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
7,993,741'Preventing damage with separators'20117,829,424'Package configuration and manufacturing method enabling the addition of decoupling capacitors to standard package designs'20107,791,210'Semiconductor package having discrete non-active electrical components incorporated into the package'20107,508,062'Package configuration and manufacturing method enabling the addition of decoupling capacitors to standard package designs'20097,414,322'High speed interface design'20087,319,272'Ball assignment system'20087,298,036'Scaling of functional assignments in packages'20077,267,880'Presence indicator for removable transparent film'20077,062,742'Routing structure for transceiver core'20067,051,434'Designing a ball assignment for a ball grid array package'20066,963,129'Multi-chip package having a contiguous heat spreader assembly'20056,858,930'Multi chip module'20056,791,177'Integrated circuit packaging that uses guard conductors to isolate noise-sensitive signals within the package substrate'20046,768,386'Dual clock package option'20046,762,366'Ball assignment for ball grid array package'20046,744,130'Isolated stripline structure'20046,701,270'Method for reliability testing leakage characteristics in an electronic circuit and a testing device for accomplishing the source'20046,680,532'Multi chip module'20046,534,968'Integrated circuit test vehicle'20036,459,049'High density signal routing'20026,445,066'Splitting and assigning power planes'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2008Patents assigned to LSI LOGIC CORP (14)· patent assignee history
2002–2010Based in Fremont, CA, US· patent location history
2007–2010Patents assigned to LSI CORP (5)· patent assignee history
2007–2011Patents assigned to CARDINAL CG CO (2)· patent assignee history
2007–2011Based in Avoca, WI, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 14 | 2002–2008 |
| LSI CORP | 5 | 2007–2010 |
| CARDINAL CG CO | 2 | 2007–2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 19 | 2002–2010 |
| Avoca, WI, US | 2 | 2007–2011 |