Inventor

Wen-Yi Hsieh

Inventor
Hsinchu, TW

Overview

89→
Patents
1999–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 89 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
G01RMeasuring electric variables11%
H01RElectrically-conductive connections11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H05KPrinted circuits8%
H10BElectronic memory devices8%
G02BOptical elements, systems or apparatus7%
G11CStatic stores5%
C23CCoating metallic material2%
PatentTitleYear
10,938,298Power controller of load power detection20219,716,346'Electrical connector with metallic shell functioned as negative terminal'20179,685,733'Magnetic connector assembly'20179,419,377'Dual orientation electrical connector assembly'2016D0761205'Electrical connector'20169,190,749'Electrical connector and electrical contacts of the same'20159,110,096'Test socket with lower and upper retaining cover'20158,936,480'Electrical connector for FPC'20158,926,194'Optical board having separated light circuit holding member and optical layer'20158,545,110'Electrical socket having optical module'20138,535,078'Electrical connector with a cover transitionally assembled on an inclined sliding slot'20138,488,926'Photoelectric connector assembly with a lens member having lenses at opposite faces thereof'20138,439,576'Photoelectric connector assembly'20138,437,586'Photoelectric connection system with waveguides'20138,434,949'Optical fiber connector'20138,430,574'Optical fiber connector with reference hole'20138,369,026'Non-spherical lens module for easy manufactory'20138,342,870'Burn-in-test socket incorporating with actuating mechanism perfecting leveling of driving plate'20138,235,601'Optical fiber connector configured with separated seat member and lens member'20128,174,904'Memory array and method of operating one of a plurality of memory cells'20128,096,822'IC socket having restraining mechanism'20128,094,493'Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control'20128,038,452'Test socket with discrete guiding posts defining side walls'20117,972,159'Electrical connector for test socket'20117,972,184'Contact for burn-in socket'20117,963,778'Burn-in socket with plated contacts'20117,956,631'Test socket for testing semiconductor package'20117,946,881'Socket assembly with heat sink module'20117,922,512'Socket connector having movable frame with actuating member'20117,878,837'Socket connector having improved actuating mechanism for driving moving plate'20117,878,821'IC socket having improved latch device'20117,867,005'IC socket having improved latch devices'20117,845,988'Electrical connector contact'20107,841,864'Electrical contact for socket connector'20107,828,576'Burn-in test socket having cover with floatable pusher'20107,830,723'Nitride read-only memory cell and nitride read-only memory array'20107,819,686'Burn-in socket'20107,815,440'Electrical contact with interlocking arrangement'20107,789,671'Electrical contact with overlapping structure'20107,789,717'Electrical connector'20107,785,124'Electrical connector having heat sink with large dissipation area'20107,741,169'Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof'20107,670,166'Burn-in socket having roller-actuated latching members arrangement'20107,637,752'Burn-in-socket having slider arrangments'20097,559,784'IC socket'20097,535,771'Devices and methods to improve erase uniformity and to screen for marginal cells for NROM memories'20097,423,913'Structures and methods for enhancing erase uniformity in a nitride read-only memory array'20087,347,228'Method of making semiconductor devices'20087,295,471'Memory device having a virtual ground array and methods using program algorithm to improve read margin loss'20077,236,404'Structures and methods for enhancing erase uniformity in an NROM array'20077,033,899'Method of making semiconductor devices'20066,768,366'Charge pump system and clock generator'20046,524,973'Method for forming low dielectric constant layer'20036,479,344'Method of fabricating DRAM capacitor'20026,403,411'Method for manufacturing lower electrode of DRAM capacitor'20026,339,025'Method of fabricating a copper capping layer'20026,316,323'Method for forming bridge free silicide by reverse spacer'20016,287,967'Self-aligned silicide process'20016,277,721'Salicide formation process'20016,277,736'Method for forming gate'20016,255,177'Method for fabricating a salicide gate'20016,251,779'Method of forming a self-aligned silicide on a semiconductor wafer'20016,251,711'Method for forming bridge free silicide'20016,249,138'Method for testing leakage current caused self-aligned silicide'20016,245,380'Method of forming bonding pad'20016,238,989'Process of forming self-aligned silicide on source/drain region'20016,228,709'Method of fabricating hemispherical grain electrode'20016,218,284'Method for forming an inter-metal dielectric layer'20016,218,238'Method of fabricating DRAM capacitor'20016,180,451'Method of forming capacitor with a HSG layer'20016,180,484'Chemical plasma treatment for rounding tungsten surface spires'20016,174,812'Copper damascene technology for ultra large scale integration circuits'20016,174,765'Method of reducing leakage current in dielectric'20016,169,028'Method fabricating metal interconnected structure'20016,156,600'Method for fabricating capacitor in integrated circuit'20006,146,941'Method for fabricating a capacitor in a semiconductor device'20006,146,742'Barrier/glue layer on polysilicon layer'20006,083,789'Method for manufacturing DRAM capacitor'20006,080,660'Via structure and method of manufacture'20006,078,492'Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall'20006,057,189'Method of fabricating capacitor utilizing an ion implantation method'20006,048,796'Method of manufacturing multilevel metal interconnect'20006,048,788'Method of fabricating metal plug'20006,046,097'Deposition method with improved step coverage'20006,022,795'Salicide formation process'20006,001,746'Method of forming an undoped silicate glass layer on a semiconductor wafer'19995,994,183'Method for forming charge storage structure'19995,994,181'Method for forming a DRAM cell electrode'19995,897,373'Method of manufacturing semiconductor components having a titanium nitride layer'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2003Patents assigned to UNITED MICROELECTRONICS CORP (37)· patent assignee history
1999–2021Based in Taipei, TW· patent location history
2000–2010Based in Hsinchu, TW· patent location history
2004–2012Patents assigned to MACRONIX INT CO LTD (8)· patent assignee history
2007–2012Based in Tainan, TW· patent location history
2009–2016Patents assigned to HON HAI PREC IND CO LTD (37)· patent assignee history
2009–2013Based in Tu-Cheng, TW· patent location history
2012–2015Patents assigned to HSIEH WEN-YI (14)· patent assignee history
2012–2015Patents assigned to CHANG YEN-CHIH (7)· patent assignee history
2013–2017Based in New Taipei, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HON HAI PREC IND CO LTD372009–2016
UNITED MICROELECTRONICS CORP371999–2003
HSIEH WEN-YIself142012–2015
MACRONIX INT CO LTD82004–2012
CHANG YEN-CHIH72012–2015
Locations
LocationPatentsSpan
Hsinchu, TW362000–2010
Tu-Cheng, TW282009–2013
New Taipei, TW122013–2017
Taipei, TW51999–2021
Tainan, TW42007–2012