Inventor
Jeehwan Kim
Inventor
Los Angeles, CA, US
Overview
Patents· 164 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices25%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution12%
H10DInorganic electric semiconductor devices11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y02PClimate change mitigation technologies in the production or processing of goods3%
Y10TTechnical subjects covered by former us classification3%
H10HInorganic light-emitting semiconductor devices having potential barriers2%
H10KOrganic electric solid-state devices2%
PatentTitleYear
10,833,187Low resistance contact interlayer for semiconductor devices202010,833,175Formation of dislocation-free SiGe finFET using porous silicon202010,804,166Porous silicon relaxation medium for dislocation free CMOS devices202010,770,289Systems and methods for graphene based layer transfer202010,756,220Cone-shaped holes for high efficiency thin film solar cells202010,741,706Transparent conductive electrode for three dimensional photovoltaic device202010,727,367Cost-efficient high power PECVD deposition for solar cells202010,686,090Wafer bonded solar cells and fabrication methods202010,672,932Cost-efficient high power PECVD deposition for solar cells202010,651,273Leakage-free implantation-free ETSOI transistors202010,643,996III-V fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface202010,615,161III-V fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface202010,593,815Double layered transparent conductive oxide for reduced Schottky barrier in photovoltaic devices202010,580,928Substrate-free thin-film flexible photovoltaic device and fabrication method202010,559,714Resonant cavity strained III-V photodetector and LED on silicon substrate202010,541,177Porous silicon relaxation medium for dislocation free CMOS devices202010,529,891Resonant cavity strained III-V photodetector and LED on silicon substrate202010,517,155Methods and apparatus for vertically stacked multicolor light-emitting diode (LED) display201910,505,066Hybrid CZTSSe photovoltaic device201910,453,978Single crystalline CZTSSe photovoltaic device201910,439,106Light emitting diode with ZnO emitter201910,431,956Nanocavity monolayer laser monolithically integrated with LED pump201910,403,779Cost-efficient high power PECVD deposition apparatus for solar cells201910,396,182Silicon germanium-on-insulator formation by thermal mixing201910,396,229Solar cell with interdigitated back contacts formed from high and low work-function-tuned silicides of the same metal201910,388,808Cone-shaped holes for high efficiency thin film solar cells201910,388,522Selective epitaxy using epitaxy-prevention layers201910,374,159Optoelectronics integration by transfer process201910,366,881Porous fin as compliant medium to form dislocation-free heteroepitaxial films201910,355,160Atomic layer deposition for photovoltaic devices201910,347,779Three-dimensional conductive electrode for solar cell201910,319,872Cost-efficient high power PECVD deposition for solar cells201910,297,709Photovoltaic devices with an interfacial band-gap modifying structure and methods for forming the same201910,283,668Photovoltaic devices with an interfacial band-gap modifying structure and methods for forming the same201910,249,737Silicon germanium-on-insulator formation by thermal mixing201910,230,010Three-dimensional conductive electrode for solar cell201910,230,015Temperature grading for band gap engineering of photovoltaic devices201910,229,857Porous silicon relaxation medium for dislocation free CMOS devices201910,204,836Porous silicon relaxation medium for dislocation free CMOS devices201910,177,269Controllable indium doping for high efficiency CZTS thin-film solar cells201910,170,372FINFET CMOS with Si NFET and SiGe PFET201910,164,014MOSFET with ultra low drain leakage201810,157,993Low resistance contact for semiconductor devices201810,121,920Aluminum-doped zinc oxysulfide emitters for enhancing efficiency of chalcogenide solar cell201810,115,894Apparatus and methods for electrical switching201810,056,251Hetero-integration of III-N material on silicon201810,056,510Cone-shaped holes for high efficiency thin film solar cells201810,043,920Highly responsive III-V photodetectors using ZnO:Al as n-type emitter201810,038,057Junction interlayer dielectric for reducing leakage current in semiconductor devices201810,008,625Atomic layer deposition for photovoltaic devices201810,002,929Reduction of defect induced leakage in III-V semiconductor devices20189,991,113Systems and methods for fabricating single-crystalline diamond membranes20189,991,417Resonant cavity strained III-V photodetector and LED on silicon substrate20189,947,529Porous fin as compliant medium to form dislocation-free heteroepitaxial films20189,947,533Selective epitaxy using epitaxy-prevention layers20189,935,215Transparent conductive electrode for three dimensional photovoltaic device20189,929,060'Porous silicon relaxation medium for dislocation free CMOS devices'20189,917,220'Buffer layer for high performing and low light degraded solar cells'20189,916,984'Self-aligned source and drain regions for semiconductor devices'20189,917,021'Porous silicon relaxation medium for dislocation free CMOS devices'20189,917,215'Double layered transparent conductive oxide for reduced schottky barrier in photovoltaic devices'20189,911,888'Photovoltaic device having layer with varying crystallinity'20189,905,637'Reduction of defect induced leakage in III-V semiconductor devices'20189,887,265'MOSFET with ultra low drain leakage'20189,876,129Cone-shaped holes for high efficiency thin film solar cells20189,865,520'Tunable semiconductor band gap reduction by strained sidewall passivation'20189,865,509'FinFET CMOS with Si NFET and SiGe PFET'20189,818,909'LED light extraction enhancement enabled using self-assembled particles patterned surface'20179,818,901'Wafer bonded solar cells and fabrication methods'20179,806,211'Tandem solar cell with improved absorption material'20179,799,747'Low resistance contact for semiconductor devices'20179,799,792'Substrate-free thin-film flexible photovoltaic device and fabrication method'20179,786,756'Self-aligned source and drain regions for semiconductor devices'20179,768,254'Leakage-free implantation-free ETSOI transistors'20179,748,412'Highly responsive III-V photodetectors using ZnO:Al as N-type emitter'20179,741,880'Three-dimensional conductive electrode for solar cell'20179,741,890'Protective insulating layer and chemical mechanical polishing for polycrystalline thin film solar cells'20179,722,120'Bandgap grading of CZTS solar cell'20179,722,033'Doped zinc oxide as n+ layer for semiconductor devices'20179,716,195'Dry etch method for texturing silicon and device'20179,716,207'Low reflection electrode for photovoltaic devices'20179,691,847'Self-formation of high-density arrays of nanostructures'20179,673,290'Self-aligned source and drain regions for semiconductor devices'20179,666,674'Formation of large scale single crystalline graphene'20179,660,116'Nanowires formed by employing solder nanodots'20179,653,570'Junction interlayer dielectric for reducing leakage current in semiconductor devices'20179,646,832'Porous fin as compliant medium to form dislocation-free heteroepitaxial films'20179,634,164'Reduced light degradation due to low power deposition of buffer layer'20179,620,592'Doped zinc oxide and n-doping to reduce junction leakage'20179,607,952'High-z oxide nanoparticles embedded in semiconductor package'20179,601,583'Hetero-integration of III-N material on silicon'20179,583,562'Reduction of defect induced leakage in III-V semiconductor devices'20179,574,287'Gallium nitride material and device deposition on graphene terminated wafer and method of forming the same'20179,577,196'Optoelectronics integration by transfer process'20179,559,120'Porous silicon relaxation medium for dislocation free CMOS devices'20179,537,038'Solar cell made using a barrier layer between P-type and intrinsic layers'20179,536,945'MOSFET with ultra low drain leakage'20179,530,643'Selective epitaxy using epitaxy-prevention layers'20169,515,215'Efficiency restoration in a photovoltaic cell'20169,490,455'LED light extraction enhancement enabled using self-assembled particles patterned surface'20169,484,347'FinFET CMOS with Si NFET and SiGe PFET'20169,459,797'Uniformly distributed self-assembled cone-shaped pillars for high efficiency solar cells'20169,443,957'Self-aligned source and drain regions for semiconductor devices'20169,443,997'Hybrid CZTSSe photovoltaic device'20169,418,870'Silicon germanium-on-insulator formation by thermal mixing'20169,401,397'Reduction of defect induced leakage in III-V semiconductor devices'20169,394,178'Wafer scale epitaxial graphene transfer'20169,379,259'Double layered transparent conductive oxide for reduced schottky barrier in photovoltaic devices'20169,337,274'Formation of large scale single crystalline graphene'20169,337,436'Transferable transparent conductive oxide'20169,331,220'Three-dimensional conductive electrode for solar cell'20169,324,794'Self-formation of high-density arrays of nanostructures'20169,324,813'Doped zinc oxide as N+ layer for semiconductor devices'20169,324,566'Controlled spalling using a reactive material stack'20169,318,641'Nanowires formed by employing solder nanodots'20169,312,132'Method of forming high-density arrays of nanostructures'20169,306,107'Buffer layer for high performing and low light degraded solar cells'20169,231,133'Nanowires formed by employing solder nanodots'20169,214,577'Reduced light degradation due to low power deposition of buffer layer'20159,203,022'Resistive random access memory devices with extremely reactive contacts'20159,190,549'Solar cell made using a barrier layer between p-type and intrinsic layers'20159,153,729'Atomic layer deposition for photovoltaic devices'20159,123,838'Transparent conductive electrode for three dimensional photovoltaic device'20159,123,842'Photoreceptor with improved blocking layer'20159,105,854'Transferable transparent conductive oxide'20159,105,805'Enhancing efficiency in solar cells by adjusting deposition power'20159,096,050'Wafer scale epitaxial graphene transfer'20159,099,664'Transferable transparent conductive oxide'20159,093,290'Self-formation of high-density arrays of nanostructures'20159,070,617'Reduced S/D contact resistance of III-V mosfet using low temperature metal-induced crystallization of n+ Ge'20159,059,013'Self-formation of high-density arrays of nanostructures'20159,059,271'Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation'20159,059,272'Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation'20159,040,340'Temperature grading for band gap engineering of photovoltaic devices'20159,040,428'Formation of metal nanospheres and microspheres'20159,035,282'Formation of large scale single crystalline graphene'20158,933,456'Germanium-containing release layer for transfer of a silicon layer to a substrate'20158,927,857'Silicon: hydrogen photovoltaic devices, such as solar cells, having reduced light induced degradation and method of making such devices'20158,916,409'Photovoltaic device using nano-spheres for textured electrodes'20148,916,451'Thin film wafer transfer and structure for electronic devices'20148,901,695'High efficiency solar cells fabricated by inexpensive PECVD'20148,889,466'Protective insulating layer and chemical mechanical polishing for polycrystalline thin film solar cells'20148,889,456'Method of fabricating uniformly distributed self-assembled solder dot formation for high efficiency solar cells'20148,878,055'Efficient nanoscale solar cell and fabrication method'20148,859,321'Mixed temperature deposition of thin film silicon tandem cells'20148,846,440'Germanium photodetector'20148,841,162'Germanium photodetector'20148,841,544'Uniformly distributed self-assembled solder dot formation for high efficiency solar cells'20148,828,504'Deposition of hydrogenated thin film'20148,822,317'Self-aligned III-V MOSFET diffusion regions and silicide-like alloy contact'20148,735,210'High efficiency solar cells fabricated by inexpensive PECVD'20148,685,858'Formation of metal nanospheres and microspheres'20148,679,947'Self-formation of high-density defect-free and aligned nanostructures'20148,628,996'Uniformly distributed self-assembled cone-shaped pillars for high efficiency solar cells'20148,628,999'Solar cell made in a single processing chamber'20148,624,361'Self-formation of high-density defect-free and aligned nanostructures'20148,617,938'Device and method for boron diffusion in semiconductors'20138,614,116'Germanium photodetector'20138,536,043'Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge'20138,304,272'Germanium photodetector'20128,298,923'Germanium-containing release layer for transfer of a silicon layer to a substrate'20128,039,371'Reduced defect semiconductor-on-insulator hetero-structures'20117,935,612'Layer transfer using boron-doped SiGe layer'20117,754,008'Method of forming dislocation-free strained thin films'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2020Based in Los Angeles, CA, US· patent location history
2011–2020Patents assigned to IBM (151)· patent assignee history
2011Based in Yorktown Heights, NY, US· patent location history
2012–2019Patents assigned to KIM JEEHWAN (32)· patent assignee history
2012–2019Patents assigned to SADANA DEVENDRA K (28)· patent assignee history
2012–2018Patents assigned to FOGEL KEITH E (13)· patent assignee history
2012–2020Based in White Plains, NY, US· patent location history
2014–2019Patents assigned to HONG AUGUSTIN J (19)· patent assignee history
2016–2020Based in Cambridge, MA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 151 | 2011–2020 |
| KIM JEEHWANself | 32 | 2012–2019 |
| SADANA DEVENDRA K | 28 | 2012–2019 |
| HONG AUGUSTIN J | 19 | 2014–2019 |
| FOGEL KEITH E | 13 | 2012–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Angeles, California, US | 90 | 2010–2020 |
| Cambridge, Massachusetts, US | 37 | 2016–2020 |
| White Plains, New York, US | 35 | 2012–2020 |
| Yorktown Heights, New York, US | 2 | 2011 |