Inventor
Sung-Shan Tai
Inventor
San Jose, CA, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices55%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H01LSemiconductor devices13%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G11CStatic stores3%
H10BElectronic memory devices3%
PatentTitleYear
9,716,156'Device structure and manufacturing method using HDP deposited source-body implant block'20179,337,329'Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source'20169,214,545'Dual gate oxide trench MOSFET with channel stop trench'20159,024,378'Device structure and manufacturing method using HDP deposited source-body implant block'20159,006,053'Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching'20159,000,514'Fabrication of trench DMOS device having thick bottom shielding oxide'20158,907,416'Dual gate oxide trench MOSFET with channel stop trench'20148,847,306'Direct contact in trench with three-mask shield gate process'20148,835,251'Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process'20148,748,268'Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching'20148,709,895'Manufacturing method power semiconductor device'20148,643,094'Method of forming a self-aligned contact opening in MOSFET'20148,536,646'Trench type power transistor device'20138,524,558'Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET'20138,507,362'Process of forming ultra thin wafers having an edge support ring'20138,471,368'Polysilicon control etch back indicator'20138,394,702'Method for making dual gate oxide trench MOSFET with channel stop using three or four masks process'20138,372,708'Device structure and manufacturing method using HDP deposited using deposited source-body implant block'20138,334,566'Semiconductor power device having shielding electrode for improving breakdown voltage'20128,252,647'Fabrication of trench DMOS device having thick bottom shielding oxide'20128,236,653'Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions'20128,193,061'Polysilicon control etch-back indicator'20128,187,939'Direct contact in trench with three-mask shield gate process'20128,105,905'Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions'20128,058,687'Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET'20118,053,315'Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer'20118,048,775'Process of forming ultra thin wafers having an edge support ring'20118,035,159'Device structure and manufacturing method using HDP deposited source-body implant block'20118,022,482'Device configuration of asymmetrical DMOSFET with schottky barrier source'20118,008,151'Shallow source MOSFET'20117,932,148'Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT)'20117,928,507'Polysilicon control etch-back indicator'20117,875,541'Shallow source MOSFET'20117,855,422'Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process'20107,829,941'Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions'20107,824,977'Completely decoupled high voltage and low voltage transistor manufacturing processes'20107,805,687'One-time programmable (OTP) memory cell'20107,667,264'Shallow source MOSFET'20107,632,733'Polysilicon control etch-back indicator'20097,492,005'Excessive round-hole shielded gate trench (SGT) MOSFET devices and manufacturing processes'20097,256,446'One time programmable memory cell'20076,509,233'Method of making trench-gated MOSFET having cesium gate oxide layer'20036,277,695'Method of forming vertical planar DMOSFET with self-aligned contact'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2017Based in San Jose, CA, US· patent location history
2007–2017Patents assigned to ALPHA & OMEGA SEMICONDUCTOR (35)· patent assignee history
2010Based in Sunnyvale, CA, US· patent location history
2011–2016Patents assigned to TAI SUNG-SHAN (22)· patent assignee history
2011–2016Patents assigned to HU YONGZHONG (6)· patent assignee history
2012–2015Patents assigned to CHANG HONG (6)· patent assignee history
2012–2015Patents assigned to BHALLA ANUP (5)· patent assignee history
2014Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALPHA & OMEGA SEMICONDUCTOR | 35 | 2007–2017 |
| TAI SUNG-SHANself | 22 | 2011–2016 |
| CHANG HONG | 6 | 2012–2015 |
| HU YONGZHONG | 6 | 2011–2016 |
| BHALLA ANUP | 5 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 41 | 2001–2017 |
| Hsinchu, TW | 1 | 2014 |
| Sunnyvale, California, US | 1 | 2010 |