Inventor
Y. Mohammed Kasem
Inventor
Santa Clara, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1050%
H10DInorganic electric semiconductor devices17%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
H01GCapacitors10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H01LSemiconductor devices2%
LOC132%
PatentTitleYear
9,136,060'Precision high-frequency capacitor formed on semiconductor substrate'20158,324,711'Precision high-frequency capacitor formed on semiconductor substrate'20128,004,063'Precision high-frequency capacitor formed on semiconductor substrate'20117,595,547'Semiconductor die package including cup-shaped leadframe'20097,589,396'Chip scale surface mount package for semiconductor device and process of fabricating the same'20097,211,877'Chip scale surface mount package for semiconductor device and process of fabricating the same'20077,151,036'Precision high-frequency capacitor formed on semiconductor substrate'20066,909,170'Semiconductor assembly with package using cup-shaped lead-frame'20056,876,061'Chip scale surface mount package for semiconductor device and process of fabricating the same'20056,744,124'Semiconductor die package including cup-shaped leadframe'20046,621,142'Precision high-frequency capacitor formed on semiconductor substrate'20036,621,143'Precision high-frequency capacitor on semiconductor substrate'20036,562,647'Chip scale surface mount package for semiconductor device and process of fabricating the same'2003D0472528'Semiconductor chip package'20036,538,300'Precision high-frequency capacitor formed on semiconductor substrate'2003D0466873'Semiconductor chip package'20026,441,475'Chip scale surface mount package for semiconductor device and process of fabricating the same'20026,392,290'Vertical structure for semiconductor wafer-level chip scale packages'20026,316,287'Chip scale surface mount packages for semiconductor device and process of fabricating the same'20016,271,060'Process of fabricating a chip scale surface mount package for semiconductor device'20016,249,041'IC chip package with directly connected leads'20016,066,890'Separate circuit devices in an intra-package configuration and assembly techniques'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2005Patents assigned to SILICONIX INC (7)· patent assignee history
2000–2015Based in Santa Clara, CA, US· patent location history
2001–2012Patents assigned to VISHAY INTERTECHNOLOGY INC (10)· patent assignee history
2006–2015Patents assigned to VISHAY SILICONIX (5)· patent assignee history
2012–2015Patents assigned to GOLDBERGER HAIM (2)· patent assignee history
2012–2015Patents assigned to KASEM Y MOHAMMED (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| VISHAY INTERTECHNOLOGY INC | 10 | 2001–2012 |
| SILICONIX INC | 7 | 2000–2005 |
| VISHAY SILICONIX | 5 | 2006–2015 |
| GOLDBERGER HAIM | 2 | 2012–2015 |
| KASEM Y MOHAMMEDself | 2 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 22 | 2000–2015 |