Inventor
John G. Gaudiello
Inventor
Poughkeepsie, NY, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H05KPrinted circuits12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
Y10TTechnical subjects covered by former us classification12%
C23CCoating metallic material11%
H10DInorganic electric semiconductor devices10%
H01LSemiconductor devices7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
B82YSpecific uses or applications of nanostructures4%
G01NInvestigating or analysing materials by determining their chemical or physical properties2%
PatentTitleYear
10,943,902Forming strained channels for CMOS device fabrication202110,756,088Method and structure of forming strained channels for CMOS device fabrication202010,685,886Fabrication of logic devices and power devices on the same substrate202010,593,672Method and structure of forming strained channels for CMOS device fabrication202010,170,548Integrated capacitors with nanosheet transistors20199,985,097Integrated capacitors with nanosheet transistors20187,932,167'Phase change memory cell with vertical transistor'20117,750,406'Design structure incorporating a hybrid substrate'20107,699,996'Sidewall image transfer processes for forming multiple line-widths'20107,651,902'Hybrid substrates and methods for forming such hybrid substrates'20107,560,692'Method of TEM sample preparation for electron holography for semiconductor devices'20097,214,935'Transmission electron microscopy sample preparation method for electron holography'20077,015,469'Electron holography method'20067,007,378'Process for manufacturing a printed wiring board'20066,759,597'Wire bonding to dual metal covered pad surfaces'20046,646,345'Method for forming Co-W-P-Au films'20036,519,845'Wire bonding to dual metal covered pad surfaces'20036,395,164'Copper seed layer repair technique using electroless touch-up'20026,383,617'Method for electroless gold deposition in the presence of a palladium seeder and article produced thereby'20026,358,832'Method of forming barrier layers for damascene interconnects'20026,335,104'Method for preparing a conductive pad for electrical connection and conductive pad formed'20026,323,128'Method for forming Co-W-P-Au films'20016,162,365'Pd etch mask for copper circuitization'20006,153,935'Dual etch stop/diffusion barrier for damascene interconnects'20006,086,946'Method for electroless gold deposition in the presence of a palladium seeder and article produced thereby'20006,042,889'Method for electrolessly depositing a metal onto a substrate using mediator ions'20005,616,422'Metallized substrate'19975,562,760'Plating bath, and corresponding method, for electrolessly depositing a metal onto a substrate, and resulting metallized substrate'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2021Patents assigned to IBM (28)· patent assignee history
1996–2004Based in Apalachin, NY, US· patent location history
2000–2021Based in Poughkeepsie, NY, US· patent location history
2009Patents assigned to DONGBU ELECTRONICS CO LTD (1)· patent assignee history
2010–2019Based in Waterford, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 28 | 1996–2021 |
| DONGBU ELECTRONICS CO LTD | 1 | 2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 18 | 2000–2021 |
| Waterford, New York, US | 5 | 2010–2019 |
| Apalachin, New York, US | 5 | 1996–2004 |