Inventor
Minh H. Tong
Inventor
Essex Junction, VT, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices41%
H03KPulse technique10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G01RMeasuring electric variables6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
G06FElectric digital data processing4%
G06KGraphical data reading3%
G06TImage data processing or generation, in general3%
G06VImage or video recognition or understanding3%
PatentTitleYear
11,037,282Detection of clarity markings in gemstones202110,909,705System and method for assessing an image sentiment20217,266,663'Automatic cache activation and deactivation for power reduction'20076,838,323'Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure'20056,664,150'Active well schemes for SOI technology'20036,552,396'Matched transistors and methods for forming the same'20036,528,846'Asymmetric high voltage silicon on insulator device design for input output circuits'20036,512,269'High-voltage high-speed SOI MOSFET'20036,498,058'SOI pass-gate disturb solution'20026,475,838'Methods for forming decoupling capacitors'20026,469,350'Active well schemes for SOI technology'20026,459,106'Dynamic threshold voltage devices with low gate to substrate resistance'20026,455,766'Contact-less probe of semiconductor wafers'20026,436,744'Method and structure for creating high density buried contact for use with SOI processes for high performance logic'20026,437,594'SOI pass gate leakage monitor'20026,429,056'Dynamic threshold voltage devices with low gate to substrate resistance'20026,424,174'Low leakage logic gates'20026,404,236'Domino logic circuit having multiplicity of gate dielectric thicknesses'20026,400,171'Method and system for processing integrated circuits'20026,365,484'Method of forming semiconductor device with decoupling capacitance'20026,333,230'Scalable high-voltage devices'20016,300,785'Contact-less probe of semiconductor wafers'20016,249,028'Operable floating gate contact for SOI with high Vt well'20016,249,029'Device method for enhanced avalanche SOI CMOS'20016,239,649'Switched body SOI (silicon on insulator) circuits and fabrication method therefor'20016,239,591'Method and apparatus for monitoring SOI hysterises effects'20016,200,843'High-voltage, high performance FETs'20016,191,451'Semiconductor device with decoupling capacitance'20016,171,918'Depleted poly mosfet structure and method'20016,100,153'Reliable diffusion resistor and diffusion capacitor'20006,100,564'SOI pass-gate disturb solution'20006,097,068'Semiconductor device fabrication method and apparatus using connecting implants'20006,088,206'Clamp circuit to limit overdrive of off chip driver'20006,057,204'Method of making a noise-isolated buried resistor by implanting a first well with a mask and then implanting an opposite conductivity well with a larger opening in the mask'20006,057,184'Semiconductor device fabrication method using connecting implants'20006,054,354'High voltage field effect transistors with selective gate depletion'20006,011,419'Decoupling scheme for mixed voltage integrated circuits'20005,973,508'Voltage translation circuit for mixed voltage applications'19995,972,745'Method or forming self-aligned halo-isolated wells'19995,959,335'Device design for enhanced avalanche SOI CMOS'19995,883,566'Noise-isolated buried resistor'19995,878,094'Noise detection and delay receiver system'19995,874,836'High reliability I/O stacked fets'19995,831,452'Leak tolerant low power dynamic circuits'19985,672,994'Antifuse circuit using standard MOSFET devices'19975,629,544'Semiconductor diode with silicide films and trench isolation'19975,543,650'Electrostatic discharge protection circuit employing a mosfet device'19965,528,188'Electrostatic discharge suppression circuit employing low-voltage triggering silicon-controlled rectifier'19965,485,095'Fabrication test circuit and method for signalling out-of-spec resistance in integrated circuit structure'19964,811,298'Decoding circuit arrangement for redundant semiconductor storage systems'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2021Patents assigned to IBM (49)· patent assignee history
1989–2005Based in Essex Junction, VT, US· patent location history
1996–2002Based in Essex, VT, US· patent location history
2002–2007Based in Raleigh, NC, US· patent location history
2002–2003Based in Fuquay-Varina, NC, US· patent location history
2021Patents assigned to BOOZ ALLEN HAMILTON INC (1)· patent assignee history
2021Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 49 | 1989–2021 |
| BOOZ ALLEN HAMILTON INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 28 | 1989–2005 |
| Essex, VT, US | 13 | 1996–2002 |
| Raleigh, NC, US | 4 | 2002–2007 |
| Fuquay-Varina, NC, US | 3 | 2002–2003 |
| Austin, Texas, US | 1 | 2021 |