Inventor
Sanjeev Maheshwari
Inventor
Fremont, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique22%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses22%
H04LTransmission of digital information, e.g. telegraphic communication19%
G01RMeasuring electric variables7%
G06FElectric digital data processing7%
G11CStatic stores7%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner7%
G01KMeasuring temperature4%
G05FSystems for regulating electric or magnetic variables4%
PatentTitleYear
11,063,600Multi-stage clock generator using mutual injection for multi-phase generation202111,023,403Chip to chip interface with scalable bandwidth202110,521,391Chip to chip interface with scalable bandwidth201910,277,230Jitter reduction in clock and data recovery circuits20199,787,509'Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample'20179,231,802'Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample'20169,083,577'Sampler circuit for a decision feedback equalizer and method of use thereof'20158,451,064'Voltage-controlled oscillator module having adjustable oscillator gain and related operating methods'20138,269,533'Digital phase-locked loop'20127,826,998'System and method for measuring the temperature of a device'20107,817,761'Test techniques for a delay-locked loop receiver interface'20107,750,711'Phase select circuit with reduced hysteresis effect'20107,545,190'Parallel multiplexing duty cycle adjustment circuit with programmable range control'20097,355,489'High gain, high frequency CMOS oscillator circuit and method'20087,342,836'One time programmable latch and method'20087,319,314'Replica regulator with continuous output correction'20087,205,797'Common mode detection and dynamic correction input circuit'20077,149,114'Latch circuit and method for writing and reading volatile and non-volatile data to and from the latch'20066,768,618'Input gate protection circuit and method'20046,687,864'Macro-cell flip-flop with scan-in input'20046,657,506'Low operating voltage crystal oscillator'20036,417,696'Interface circuit for mixed voltage I/O buffer to provide gate oxide protection'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2010Patents assigned to CYPRESS SEMICONDUCTOR CORP (10)· patent assignee history
2003Based in Jaiaitaran (Pali) Rajashthan, IN· patent location history
2004Based in Santa Clara, CA, US· patent location history
2004Based in Taitaran, IN· patent location history
2006–2010Based in San Jose, CA, US· patent location history
2009–2013Patents assigned to ADVANCED MICRO DEVICES INC (4)· patent assignee history
2012–2013Patents assigned to FANG EMERSON (2)· patent assignee history
2012–2021Based in Fremont, CA, US· patent location history
2015–2017Patents assigned to NVIDIA CORP (3)· patent assignee history
2019–2021Patents assigned to APPLE INC (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CYPRESS SEMICONDUCTOR CORP | 10 | 2002–2010 |
| ADVANCED MICRO DEVICES INC | 4 | 2009–2013 |
| APPLE INC | 4 | 2019–2021 |
| NVIDIA CORP | 3 | 2015–2017 |
| FANG EMERSON | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 9 | 2012–2021 |
| San Jose, California, US | 9 | 2006–2010 |
| Santa Clara, California, US | 1 | 2004 |
| Taitaran, IN | 1 | 2004 |
| Jaiaitaran (Pali) Rajashthan, IN | 1 | 2003 |