Inventor
PATRICK MORROW
Inventor
US
Overview
Patents· 94 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices27%
H10DInorganic electric semiconductor devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
B82YSpecific uses or applications of nanostructures7%
H10BElectronic memory devices3%
G06FElectric digital data processing1%
H10NElectric solid-state devices not otherwise provided for1%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution1%
G11CStatic stores1%
PatentTitleYear
12,598,814Lateral diodes in stacked transistor technologies202612,581,938Package architecture for quasi-monolithic chip with backside power202612,581,717Frontside and backside epi contact202612,557,259Backside shunt contact for improved integrated circuit layout202612,506,059Vertically spaced intra-level interconnect line metallization for integrated circuit devices202512,446,204SRAM with P-type access transistors and complementary field-effect transistor technology202512,369,399Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure202512,342,614Asymmetric gate structures and contacts for stacked transistors202512,310,044Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices202512,288,810Backside contact structures and fabrication for metal on both sides of devices202512,255,137Sideways vias in isolation areas to contact interior layers in stacked devices202512,224,202Forming an oxide volume within a fin202512,199,143Gate-all-around integrated circuit structures having removed substrate202512,176,323Microelectronic assemblies202412,148,806Stacked source-drain-gate connection and process for forming such202412,107,085Interconnect techniques for electrically connecting source/drain regions of stacked transistors202412,100,623Vertically stacked finFETs and shared gate patterning202412,100,762Wrap-around source/drain method of making contacts for backside metals202412,100,761Wrap-around source/drain method of making contacts for backside metals202412,057,494Stacked transistors202412,051,723PN-body-tied field effect transistors202412,020,929Epitaxial layer with substantially parallel sides202411,996,362Integrated circuit device with crenellated metal trace layout202411,996,411Stacked forksheet transistors202411,990,899Multi-level spin logic202411,948,831Apparatus with multi-wafer based device and method for forming such202411,948,874Vertically spaced intra-level interconnect line metallization for integrated circuit devices202411,942,416Sideways vias in isolation areas to contact interior layers in stacked devices202411,942,526Integrated circuit contact structures202411,935,891Non-silicon N-type and P-type stacked transistors for integrated circuit devices202411,935,933Backside contact structures and fabrication for metal on both sides of devices202411,916,118Stacked source-drain-gate connection and process for forming such202411,894,372Stacked trigate transistors with dielectric isolation and process for forming such202411,894,262Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures202411,869,894Metallization structures for stacked device connectivity and their methods of fabrication202411,854,894Integrated circuit device structures and double-sided electrical testing202311,830,933Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach202311,798,838Capacitance reduction for semiconductor devices based on wafer bonding202311,776,898Sidewall interconnect metallization structures for integrated circuit devices202311,769,814Device including air gapping of gate spacers and other dielectrics and process for providing such202311,764,263Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches202311,764,104Forming an oxide volume within a fin202311,749,649Composite IC chips including a chiplet embedded within metallization layers of a host IC chip202311,742,346Interconnect techniques for electrically connecting source/drain regions of stacked transistors202311,721,649Microelectronic assemblies202311,699,637Vertically stacked transistor devices with isolation wall structures containing an electrical conductor202311,694,986Vias in composite IC chip structures202311,676,966Stacked transistors having device strata with different channel widths202311,664,373Isolation walls for vertically stacked transistor structures202311,664,377Forksheet transistor architectures202311,658,221Backside contact structures and fabrication for metal on both sides of devices202311,658,072Vertically stacked transistors in a fin202311,658,183Metallization structures under a semiconductor device layer202311,646,352Stacked source-drain-gate connection and process for forming such202311,640,961III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts202311,616,056Vertical diode in stacked transistor architecture202311,616,015Integrated circuit device with back-side interconnection to deep source/drain semiconductor202311,605,556Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures202311,605,565Three dimensional integrated circuits with stacked transistors202311,594,452Techniques for revealing a backside of an integrated circuit device, and associated configurations202311,594,533Stacked trigate transistors with dielectric isolation between first and second semiconductor fins202311,594,524Fabrication and use of through silicon vias on double sided interconnect device202311,573,798Stacked transistors with different gate lengths in different device strata202311,569,238Vertical memory cells202311,552,104Stacked transistors with dielectric between channels of different device strata202311,532,719Transistors on heterogeneous bonding layers202211,522,072Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices202211,515,3183D floating-gate multiple-input device202211,482,621Vertically stacked CMOS with upfront M0 interconnect202211,462,568Stacked thin film transistors202211,444,166Backside source/drain replacement for semiconductor devices with metallization on both sides202211,437,405Transistors stacked on front-end p-type transistors202211,430,814Metallization structures for stacked device connectivity and their methods of fabrication202211,424,160Self-aligned local interconnects202211,404,319Vertically stacked finFETs and shared gate patterning202211,398,479Heterogeneous Ge/III-V CMOS transistor structures202211,393,818Stacked transistors with Si PMOS and high mobility thin film transistor NMOS202211,393,777Microelectronic assemblies202211,387,238Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices202211,380,684Stacked transistor architecture including nanowire or nanoribbon thin film transistors202211,374,004Pedestal fin structure for stacked transistor integration202211,348,897Microelectronic assemblies202211,342,227Stacked transistor structures with asymmetrical terminal interconnects202211,328,951Transistor cells including a deep via lined wit h a dielectric material202211,264,405Semiconductor diodes employing back-side semiconductor or metal202211,264,493Wrap-around source/drain method of making contacts for backside metals202211,257,738Vertically stacked transistor devices with isolation wall structures containing an electrical conductor202211,257,929Stacked transistors202211,251,156Fabrication and use of through silicon vias on double sided interconnect device202211,239,236Forksheet transistor architectures202211,239,232Isolation walls for vertically stacked transistor structures202211,205,630Vias in composite IC chip structures202111,201,221Backside contact structures and fabrication for metal on both sides of devices202111,139,241Integrated circuit device with crenellated metal trace layout2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (94)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 94 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 94 | 2021–2026 |