Inventor
David L. Bergeron
Inventor
Winooski, VT, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices38%
H01JElectric discharge tubes or discharge lamps12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
B82YSpecific uses or applications of nanostructures6%
H03KPulse technique6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
C23FNon-mechanical removal of metallic material from surface3%
G02BOptical elements, systems or apparatus3%
G05DSystems for controlling or regulating non-electric variables3%
PatentTitleYear
7,025,892'Method for creating gated filament structures for field emission displays'20066,278,829'Optical fiber routing and support apparatus'20015,897,414'Technique for increasing manufacturing yield of matrix-addressable device'19995,665,421'Method for creating gated filament structures for field emission displays'19975,578,185'Method for creating gated filament structures for field emision displays'19964,547,793'Trench-defined semiconductor structure'19854,446,611'Method of making a saturation-limited bipolar transistor device'19844,412,308'Programmable bipolar structures'19834,395,812'Forming an integrated circuit'19834,390,890'Saturation-limited bipolar transistor device'19834,373,166'Schottky Barrier diode with controlled characteristics'19834,357,178'Schottky barrier diode with controlled characteristics and fabrication method'19824,344,222'Bipolar compatible electrically alterable read-only memory'19824,326,212'Structure and process for optimizing the characteristics of I.sup.2 L devices'19824,314,267'Dense high performance JFET compatible with NPN transistor formation and merged BIFET'19824,229,753'Voltage compensation of temperature coefficient of resistance in an integrated circuit resistor'19804,201,800'Hardened photoresist master image mask process'19804,157,268'Localized oxidation enhancement for an integrated injection logic circuit'19794,110,126'NPN/PNP Fabrication process with improved alignment'1978Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1978–1985Patents assigned to IBM (14)· patent assignee history
1978–1982Based in Manassas, VA, US· patent location history
1980–1985Based in Winooski, VT, US· patent location history
1996Patents assigned to SILICON VIDEO CORP (1)· patent assignee history
1996–2006Based in San Jose, CA, US· patent location history
1997–2006Patents assigned to CANDESCENT TECH CORP (3)· patent assignee history
2001Patents assigned to MARCONI COMM INC (1)· patent assignee history
2001Based in Bedford, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 14 | 1978–1985 |
| CANDESCENT TECH CORP | 3 | 1997–2006 |
| MARCONI COMM INC | 1 | 2001 |
| SILICON VIDEO CORP | 1 | 1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Winooski, VT, US | 10 | 1980–1985 |
| San Jose, California, US | 4 | 1996–2006 |
| Manassas, Virginia, US | 4 | 1978–1982 |
| Bedford, Texas, US | 1 | 2001 |