Inventor
ARIJIT RAYCHOWDHURY
Inventor
Hillsboro, OR, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores19%
G06FElectric digital data processing12%
H03KPulse technique12%
G05FSystems for regulating electric or magnetic variables10%
H10DInorganic electric semiconductor devices7%
G01KMeasuring temperature5%
G10LSpeech analysis techniques or speech synthesis5%
H01LSemiconductor devices5%
H10BElectronic memory devices5%
H10NElectric solid-state devices not otherwise provided for5%
PatentTitleYear
10,712,759System and method for enhancing bandwidth of low-dropout regulators using power transmission lines for high speed input output drivers20209,870,012'Digitally phase locked low dropout regulator apparatus and system using ring oscillators'20189,722,606'Digital clamp for state retention'20179,633,654'Low power voice detection'20179,577,641'Spin transfer torque based memory elements for programmable device arrays'20179,484,917'Digital clamp for state retention'20169,472,748'Balancing energy barrier between states in perpendicular magnetic tunnel junctions'20169,455,011'Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current'20169,270,278'Spin transfer torque based memory elements for programmable device arrays'20169,236,562'Balancing energy barrier between states in perpendicular magnetic tunnel junctions'20169,121,768'Thermal sensor device'20158,901,819'Multi-supply sequential logic unit'20148,725,506'Speech audio processing'20148,467,263'Memory write operation methods and circuits'20138,389,976'Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby'20138,096,707'Thermal sensor device'20128,094,505'Method and system to lower the minimum operating voltage of a memory array'20127,961,498'Leakage compensation circuit for Dynamic Random Access Memory (DRAM) cells'20117,298,838'Adaptive cancellation network system and method for digital subscriber line'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2013Based in West Lafayette, IN, US· patent location history
2011–2018Patents assigned to INTEL CORP (17)· patent assignee history
2011–2018Based in Hillsboro, OR, US· patent location history
2012–2017Patents assigned to RAYCHOWDHURY ARIJIT (12)· patent assignee history
2013–2016Patents assigned to DE VIVEK (2)· patent assignee history
2014–2017Patents assigned to TSCHANZ JAMES W (4)· patent assignee history
2014–2017Patents assigned to BELTMAN WILLEM M (2)· patent assignee history
2016–2017Based in Duluth, GA, US· patent location history
2020Based in Atlanta, GA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 17 | 2011–2018 |
| RAYCHOWDHURY ARIJITself | 12 | 2012–2017 |
| TSCHANZ JAMES W | 4 | 2014–2017 |
| BELTMAN WILLEM M | 2 | 2014–2017 |
| DE VIVEK | 2 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 13 | 2011–2018 |
| Duluth, Georgia, US | 3 | 2016–2017 |
| West Lafayette, IN, US | 2 | 2007–2013 |
| Atlanta, Georgia, US | 1 | 2020 |