Inventor
CHRISTOPHE VINCENT ANTOINE LAURENT
Inventor
IT
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing36%
G11CStatic stores33%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
H03MCoding8%
H10BElectronic memory devices5%
H01LSemiconductor devices2%
H04BTransmission2%
H04WWireless communication networks2%
H10DInorganic electric semiconductor devices2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
12,578,781Bank configurable power modes202612,542,567Fast multi-payload-length error-correcting system and methods202612,525,993Fast multi-payload-length error-correcting system and methods202612,493,521Generating a protected and balanced codeword202512,469,546Memory array seasoning202512,461,812ECC power consumption optimization in memories202512,321,610Balanced codewords for reducing a selected state in memory cells202512,300,305Parallel access in a memory array202512,288,592Performing sense operations in memory202512,260,907Shared decoder architecture for three-dimensional memory arrays202512,228,991Architecture-based power management for a memory device202512,182,432Circuit partitioning for a memory device202412,086,421Memory device with data scrubbing capability and methods202412,045,113Bank configurable power modes202412,039,176Providing multiple error correction code protection levels in memory202411,967,372Shared decoder architecture for three-dimensional memory arrays202411,914,476Generating a protected and balanced codeword202411,915,740Parallel access in a memory array202411,811,424Fixed weight codewords for ternary memory cells202311,742,047Shared error correction coding circuitry202311,740,678Architecture-based power management for a memory device202311,733,913Balancing data for storage in a memory device202311,687,411Generating a balanced codeword protected by an error correction code202311,567,831Generating a protected and balanced codeword202311,494,264Generating a protected and balanced codeword202211,355,162Active boundary quilt architecture memory202211,262,937Balancing data for storage in a memory device202211,243,596Architecture-based power management for a memory device202211,237,906Generating a balanced codeword protected by an error correction code202211,205,469Power domain switches for switching power reduction202111,152,039Input/output line sharing for memory arrays202111,144,228Circuit partitioning for a memory device2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (31)· patent assignee history
2021–2026Based in IT· patent location history
2025Patents assigned to LODESTAR LICENSING GROUP LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 31 | 2021–2026 |
| LODESTAR LICENSING GROUP LLC | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| IT | 32 | 2021–2026 |