Inventor

Joseph R. Greco

Inventor

South Burlington, VT, US

Overview

2004–2019

Patent span

Electricity

Primary field (CPC H)

Patents· 15 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices33%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

H01LSemiconductor devices11%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

H01JElectric discharge tubes or discharge lamps3%

PatentTitleYear

10,211,324Vertical p-type, n-type, p-type (PNP) junction integrated circuit (IC) structure2019 9,837,514Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure2017 9,735,259'Method to build vertical PNP in a BiCMOS technology with improved speed'2017 9,324,828'Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming'2016 9,214,318'Electromagnetic electron reflector'2015 8,492,294'Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic suppressing region'2013 8,299,537'Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region'2012 7,777,302'Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structure'2010 7,732,303'Method for recycling of ion implantation monitor wafers'2010 7,700,488'Recycling of ion implantation monitor wafers'2010 7,247,924'Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures'2007 7,008,852'Discontinuous dielectric interface for bipolar transistors'2006 6,939,771'Discontinuous dielectric interface for bipolar transistors'2005 6,703,283'Discontinuous dielectric interface for bipolar transistors'2004 6,682,992'Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2019Patents assigned to IBM (15)· patent assignee history

2004–2019Based in South Burlington, VT, US· patent location history

2012–2013Patents assigned to GRECO JOSEPH R (2)· patent assignee history

2012–2013Patents assigned to MUNGER KEVIN (2)· patent assignee history

2012–2013Patents assigned to PHELPS RICHARD A (2)· patent assignee history

2012–2013Patents assigned to ROBBINS JENNIFER C (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	15	2004–2019
GRECO JOSEPH Rself	2	2012–2013
MUNGER KEVIN	2	2012–2013
PHELPS RICHARD A	2	2012–2013
ROBBINS JENNIFER C	2	2012–2013

Locations

Location	Patents	Span
South Burlington, VT, US	15	2004–2019