Inventor
Chiting Cheng
Inventor
Taichung, TW
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores47%
H10BElectronic memory devices10%
G06FElectric digital data processing7%
H01LSemiconductor devices7%
H03KPulse technique6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y10TTechnical subjects covered by former us classification4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
10,878,855Low cell voltage (LCV) memory write assist202010,872,659Memory system having write assist circuit including memory-adapted transistors202010,867,646Bit line logic circuits and methods202010,847,217Pre-charging bit lines through charge-sharing202010,847,210Memory device with fly word line202010,818,677Layout of static random access memory periphery circuit202010,811,085Dual rail device with power detector202010,762,934Leakage pathway prevention in a memory storage device202010,622,039Dual rail memory with bist circuitry, memory macro and associated hybrid power supply method202010,574,213Clock circuit and method of operating the same202010,559,333Memory macro and method of operating the same202010,553,275Device having write assist circuit including memory-adapted transistors and method for making the same202010,503,421Configurable memory storage system201910,490,263Dual rail device with power detector201910,410,715Pre-charging bit lines through charge-sharing201910,340,897Clock generating circuit and method of operating the same201910,319,421Memory macro and method of operating the same201910,281,502Maximum voltage selection circuit201910,263,621Level shifter with improved voltage difference201910,163,470Dual rail memory, memory macro and associated hybrid power supply method201810,141,045Dual rail device with power detector for controlling power to first and second power domains20189,997,219Memory macro and method of operating the same20189,959,916Dual rail memory, memory macro and associated hybrid power supply method20189,922,701'Pre-charging bit lines through charge-sharing'20189,865,335'SRAM device capable of working in multiple low voltages without loss of performance'20189,824,729'Memory macro and method of operating the same'20179,762,216'Level shifter circuit using boosting circuit'20179,666,253'Dual rail memory, memory macro and associated hybrid power supply method'20179,659,603'Power management circuit for an electronic device'20179,583,181'SRAM device capable of working in multiple low voltages without loss of performance'20179,489,991'Memory reading circuit, memory device and method of operating memory device'20169,437,281'Negative bitline boost scheme for SRAM write-assist'20169,324,413'Write assist circuit, memory device and method'20169,324,453'Memory unit and method of testing the same'20169,305,635'High density memory structure'20169,263,123'Memory device and a method of operating the same'20169,076,553'SPSRAM wrapper'20159,070,432'Negative bitline boost scheme for SRAM write-assist'20159,064,550'Method and apparatus for word line suppression'20159,025,356'Fly-over conductor segments in integrated circuits with successive load devices along a signal path'20158,923,078'Voltage divider control circuit'20148,848,461'Memory cell having flexible read/write assist and method of using'20148,816,403'Efficient semiconductor device cell layout utilizing underlying local connective features'20148,724,420'SRAM write assist apparatus'20148,675,439'Bit line voltage bias for low power memory design'20148,630,132'SRAM read and write assist apparatus'20148,437,166'Word line driver cell layout for SRAM and other semiconductor devices'20138,437,215'Memory with word-line segment access'20134,924,918'Machine for manufacturing button connector and method therefor'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990Based in Taipei, TW· patent location history
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (13)· patent assignee history
2013–2015Patents assigned to CHENG CHITING (9)· patent assignee history
2013–2015Patents assigned to CHOU CHUNG-CHENG (5)· patent assignee history
2013–2020Based in Taichung, TW· patent location history
2014–2015Patents assigned to CHANG JONATHAN TSUNG-YUNG (4)· patent assignee history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (35)· patent assignee history
2020Based in Hsinchu, TW· patent location history
2020Based in Taiching, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 35 | 2015–2020 |
| TAIWAN SEMICONDUCTOR MFG | 13 | 2013–2016 |
| CHENG CHITINGself | 9 | 2013–2015 |
| CHOU CHUNG-CHENG | 5 | 2013–2015 |
| CHANG JONATHAN TSUNG-YUNG | 4 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taichung, TW | 45 | 2013–2020 |
| Hsinchu, TW | 2 | 2020 |
| Taiching, TW | 1 | 2020 |
| Taipei, TW | 1 | 1990 |