Inventor
Joseph M. Steigerwald
Inventor
Forest Grove, OR, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices23%
H10DInorganic electric semiconductor devices22%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10BElectronic memory devices8%
G11CStatic stores4%
H10NElectric solid-state devices not otherwise provided for4%
B24BMachines, devices, or processes for grinding or polishing1%
C25FProcesses for the electrolytic removal of materials from objects1%
H05KPrinted circuits1%
PatentTitleYear
10,930,557Self-aligned contacts202110,861,851Wrap-around trench contact structure and methods of fabrication202010,854,731Heterogeneous metal line compositions for advanced integrated circuit structure fabrication202010,777,655Heterogeneous metal line compositions for advanced integrated circuit structure fabrication202010,644,064Logic chip including embedded magnetic tunnel junctions202010,629,483Self-aligned contacts202010,573,747Multi-threshold voltage devices and associated techniques and configurations202010,141,226Self-aligned contacts20189,997,563Logic chip including embedded magnetic tunnel junctions20189,972,541Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurations20189,892,967'Self-aligned contacts'20189,876,016Wrap-around trench contact structure and methods of fabrication20189,761,713'Multi-threshold voltage devices and associated techniques and configurations'20179,660,181'Logic chip including embedded magnetic tunnel junctions'20179,565,766'Formation of DRAM capacitor among metal interconnect'20179,508,821'Self-aligned contacts'20169,466,565'Self-aligned contacts'20169,219,155'Multi-threshold voltage devices and associated techniques and configurations'20159,093,513'Self-aligned contacts'20159,054,178'Self-aligned contacts'20159,041,146'Logic chip including embedded magnetic tunnel junctions'20158,441,097'Methods to form memory devices having a capacitor with a recessed electrode'20138,436,404'Self-aligned contacts'20138,334,184'Polish to remove topography in sacrificial gate layer prior to gate patterning'20127,052,996'Electrochemically polishing conductive films on semiconductor wafers'20066,103,625'Use of a polish stop layer in the formation of metal structures'20005,637,185'Systems for performing chemical mechanical planarization and process for conducting same'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997Based in Aloha, OR, US· patent location history
2000–2021Patents assigned to INTEL CORP (26)· patent assignee history
2000Based in Beaverton, OR, US· patent location history
2006–2021Based in Forest Grove, OR, US· patent location history
2012–2017Patents assigned to STEIGERWALD JOSEPH M (6)· patent assignee history
2013–2018Patents assigned to GHANI TAHIR (4)· patent assignee history
2013–2015Patents assigned to BOHR MARK T (3)· patent assignee history
2013–2015Patents assigned to HWANG JACK (3)· patent assignee history
2020Based in Hillsboro, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 26 | 2000–2021 |
| STEIGERWALD JOSEPH Mself | 6 | 2012–2017 |
| GHANI TAHIR | 4 | 2013–2018 |
| BOHR MARK T | 3 | 2013–2015 |
| HWANG JACK | 3 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Forest Grove, OR, US | 24 | 2006–2021 |
| Hillsboro, OR, US | 1 | 2020 |
| Beaverton, OR, US | 1 | 2000 |
| Aloha, OR, US | 1 | 1997 |