Inventor
Albert Bergemont
Inventor
Palo Alto, CA, US
Overview
Patents· 160 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices29%
H10DInorganic electric semiconductor devices25%
G11CStatic stores20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
H01LSemiconductor devices2%
G05FSystems for regulating electric or magnetic variables0%
G06NComputing arrangements based on specific computational models0%
PatentTitleYear
9,673,316'Vertical semiconductor device having frontside interconnections'20179,450,052'EEPROM memory cell with a coupler region and method of making the same'20169,184,113'Methods of forming coaxial feedthroughs for 3D integrated circuits'20159,129,710'Dynamic trim method for non volatile memory products'20158,975,685'N-channel multi-time programmable memory devices'20158,951,856'Low-noise, high-gain semiconductor device incorporating BCD (Bipolar-CMOS-DMOS) technology and process of making the same'20158,940,631'Methods of forming coaxial feedthroughs for 3D integrated circuits'20158,847,365'Inductors and methods for integrated circuits'20148,796,767'Low-noise, high-gain semiconductor device incorporating BCD (bipolar-CMOS-DMOS) technology'20148,686,543'3D chip package with shielded structures'20148,630,137'Dynamic trim method for non-volatile memory products'20148,405,115'Light sensor using wafer-level packaging'20138,344,478'Inductors having inductor axis parallel to substrate surface'20137,944,750'Multi-programmable non-volatile memory cell'20117,943,473'Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme'2011RE040976'Common source EEPROM and flash memory'20097,535,758'One or multiple-times programmable device'20097,324,387'Low power high density random access memory flash cells and arrays'20086,905,929'Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process'20056,830,988'Method of forming an isolation structure for an integrated circuit utilizing grown and deposited oxide'20046,606,265'Common source EEPROM and flash memory'20036,563,731'EEPROM memory cell array embedded on core CMOS'20036,525,397'Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology'20036,509,606'Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process'20036,507,516'EEPROM memory cell embedded on core CMOS for analog applications'20036,498,084'Method of forming high density EEPROM cell'20026,482,723'Method for forming self-aligned floating gates'20026,420,217'Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology'20026,414,872'Compact non-volatile memory device and memory array'20026,384,398'CMOS compatible pixel cell that utilizes a gated diode to reset the cell'20026,380,054'Schottky diode with reduced size'20026,380,571'CMOS compatible pixel cell that utilizes a gated diode to reset the cell'20026,368,917'Methods of fabricating floating gate semiconductor device with reduced erase voltage'20026,365,463'Method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up'20026,362,023'Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture'20026,362,050'Method for forming a non-volatile memory cell that eliminates substrate trenching'20026,327,187'EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming'20016,300,220'Process for fabricating isolation structure for IC featuring grown and buried field oxide'20016,277,724'Method for forming an array of sidewall-contacted antifuses having diffused bit lines'20016,271,560'Single-poly EPROM cell with CMOS compatible programming voltages'20016,262,460'Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor'20016,249,010'Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture'20016,238,979'Process for fabricating EEPROM memory cell array embedded on core CMOS'20016,236,082'Floating gate semiconductor device with reduced erase voltage'20016,229,739'Sense amplifier having a bias circuit with a reduced size'20016,225,163'Process for forming high quality gate silicon dioxide layers of multiple thicknesses'20016,218,688'Schottky diode with reduced size'20016,215,698'Flash eprom with byte-wide erasure'20016,208,557'EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming'20016,197,671'Multiple finger polysilicon gate structure and method of making'20016,190,968'Method for forming EPROM and flash memory cells with source-side injection'20016,184,552'Non-volatile memory cell with non-trenched substrate'20016,184,099'Low cost deep sub-micron CMOS process'20016,184,557'I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection'20016,180,994'Array of sidewall-contacted antifuses having diffused bit lines'20016,177,315'Method of fabricating a high density EEPROM array'20016,169,310'Electrostatic discharge protection device'20016,166,421'Polysilicon fuse that provides an open current path when programmed without exposing the fuse to the environment'20006,157,574'Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data'20006,146,962'Method for forming a DRAM cell with a stacked capacitor'20006,136,635'Method for forming a bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region'20006,137,721'Memory device having erasable frohmann-bentchkowsky EPROM cells that use a plate-to-floating gate coupled voltage during erasure'20006,137,722'Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors'20006,137,723'Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure'20006,137,724'Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages'20006,130,840'Memory cell having an erasable Frohmann-Bentchkowsky memory transistor'20006,122,204'Sense amplifier having a bias circuit with a reduced size'20006,118,157'High voltage split gate CMOS transistors built in standard 2-poly core CMOS'20006,110,797'Process for fabricating trench isolation structure for integrated circuits'20006,087,211'Method for forming a semiconductor device having non-volatile memory cells, High-voltage transistors, and low-voltage, deep sub-micron transistors'20006,083,791'Self-aligned stacked gate etch process for fabricating a two-transistor EEPROM cell'20006,080,601'Method for forming a bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region'20006,081,451'Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages'20006,078,094'Starter current source device with automatic shut-down capability and method for its manufacture'20006,078,211'Substrate biasing circuit that utilizes a gated diode to set the bias on the substrate'20006,055,185'Single-poly EPROM cell with CMOS compatible programming voltages'20006,049,202'Reference current generator with gated-diodes'20006,031,275'Antifuse with a silicide layer overlying a diffusion region'20006,011,295'Neural network active pixel cell'20006,008,508'ESD Input protection using a floating gate neuron MOSFET as a tunable trigger element'19995,998,267'Process to manufacture high density ULSI ROM array'19995,998,280'Modified recessed locos isolation process for deep sub-micron device processes'19995,994,186'Contactless flash eprom using poly silicon isolation and process of making the same'19995,982,669'EPROM and flash memory cells with source-side injection'19995,978,269'Apparatus and method for lowering the potential barrier across the source-to-well junction during the programming of non-volatile memory cells'19995,969,406'High linearity capacitor using a damascene tungsten stud as the bottom electrode'19995,962,844'Active pixel image cell with embedded memory and pixel level signal processing capability'19995,940,324'Single-poly EEPROM cell that is programmable and erasable in a low-voltage environment'19995,932,873'Capacitor-coupled bipolar active pixel sensor with integrated electronic shutter'19995,908,311'Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells'19995,889,700'High density EEPROM array using self-aligned control gate and floating gate for both access transistor and memory cell and method of operating same'19995,856,222'Method of fabricating a high density EEPROM cell'19995,847,426'Contactless flash EPROM using poly silicon isolation'19985,847,422'MOS-based active pixel sensor cell that utilizes the parasitic bipolar action of the cell to output image data'19985,837,574'Method of manufacturing a thin poly, capacitor coupled contactless imager with high resolution and wide dynamic range'19985,828,102'Multiple finger polysilicon gate structure and method of making'19985,814,856'Variable and tunable V.sub.T MOSFET with poly and/or buried diffusion'19985,808,937'Self-convergent method for programming FLASH and EEPROM memory cells that moves the threshold voltage from an erased threshold voltage range to one of a plurality of programmed threshold voltage ranges'19985,806,054'Neuron MOSFET module structure for binary logic circuits'19985,789,791'Multi-finger MOS transistor with reduced gate resistance'19985,786,623'Bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region'19985,776,795'Method of making a contactless capacitor-coupled bipolar active pixel sensor with intergrated electronic shutter'19985,761,126'Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell'19985,760,458'Bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region'19985,753,954'Single-poly neuron MOS transistor'19985,734,191'Contactless capacitor-coupled bipolar active pixel sensor with integrated electronic shutter'19985,721,170'Method of making a high-voltage MOS transistor with increased breakdown voltage'19985,710,446'Active pixel sensor cell that utilizes a parasitic transistor to reset the photodiode of the cell'19985,688,705'Method for reducing the spacing between the horizontally adjacent floating gates of a flash EPROM array'19975,615,152'Method of erasing a high density contactless flash EPROM array'19975,608,243'Single split-gate MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range'19975,604,141'Method for forming virtual-ground flash EPROM array with reduced cell pitch in the X direction'19975,604,698'Virtual-ground flash EPROM array with reduced cell pitch in the X direction'19975,594,685'Method for programming a single EPROM or flash memory cell to store multiple bits of data that utilizes a punchthrough current'19975,589,412'Method of making increased-density flash EPROM that utilizes a series of planarized, self-aligned, intermediate strips of conductive material to contact the drain regions'19965,590,068'Ultra-high density alternate metal virtual ground ROM'19965,587,949'Method for programming an ETOX EPROM or flash memory when cells of the array are formed to store multiple bits of data'19965,587,596'Single MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range'19965,576,237'Method of manufacturing a capacitor coupled contactless imager with high resolution and wide dynamic range'19965,566,044'Base capacitor coupled photosensor with emitter tunnel oxide for very wide dynamic range in a contactless imaging array'19965,566,106'Method for reducing the spacing between the horizontally-adjacent floating gates of a flash EPROM array'19965,557,567'Method for programming an AMG EPROM or flash memory when cells of the array are formed to store multiple bits of data'19965,552,619'Capacitor coupled contactless imager with high resolution and wide dynamic range'19965,512,504'Method of making a memory array with field oxide islands eliminated'19965,511,021'Method for programming a single EPROM or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction'19965,496,754'Method for preventing bit line-to-bit line leakage in the access transistor region of an AMG EPROM'19965,484,741'Method of making increased-density flash EPROM that requires less area to form the metal bit line-to-drain contacts'19965,481,493'Segment-erasable flash EPROM'19965,477,485'Method for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrate'19955,464,999'Method for programming an alternate metal/source virtual ground flash EPROM cell array'19955,460,990'Method for fabricating a segmented AMG EPROM where only every fourth bit line contacts a select transistor in a row of segment select transistors'19955,455,790'High density EEPROM cell array which can selectively erase each byte of data in each row of the array'19955,453,393'Method for forming a high density EEPROM cell array with improved access time'19955,449,633'Method for fabricating an ultra-high-density alternate metal virtual ground ROM'19955,436,478'Fast access AMG EPROM with segment select transistors which have an increased width'19955,422,844'Memory array with field oxide islands eliminated and method'19955,416,349'Increased-density flash EPROM that requires less area to form the metal bit line-to-drain contacts'19955,409,854'Method for forming a virtual-ground flash EPROM array with floating gates that are self aligned to the field oxide regions of the array'19955,402,372'High density EEPROM cell array with improved access time and method of manufacture'19955,397,725'Method of controlling oxide thinning in an EPROM or flash memory array'19955,397,726'Segment-erasable flash EPROM'19955,379,253'High density EEPROM cell array with novel programming scheme and method of manufacture'19955,371,030'Method of fabricating field oxide isolation for a contactless flash EPROM cell array'19945,346,842'Method of making alternate metal/source virtual ground flash EPROM cell array'19945,304,503'Self-aligned stacked gate EPROM cell using tantalum oxide control gate dielectric'19945,293,331'High density EEPROM cell with tunnel oxide stripe'19945,246,874'Method of making fast access AMG EPROM'19935,240,870'Stacked gate process flow for cross-point EPROM with internal access transistor'19935,225,362'Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer'19935,212,541'Contactless, 5V, high speed EPROM/flash EPROM array utilizing cells programmed using source side injection'19935,091,327'Fabrication of a high density stacked gate EPROM split cell with bit line reach-through and interruption immunity'19925,086,410'Non-erasable EPROM cell for redundancy circuit'19925,047,362'Method of making large-scale EPROM memory with a checker board pattern and an improved coupling factor'19915,016,069'Large-scale EPROM memory'19915,013,674'A method of manufacturing integrated circuits comprising EPROM memory and logic transistors'19915,012,446'Large-scale EPROM memory with a high coupling factor'19914,926,223'Dynamic memory of the integrated circuit type'19904,888,628'Dynamic memory in integrated circuit form'19894,887,238'Non-volatile memory with floating grid and without thick oxide'19894,877,483'Method for contact between two conductive or semi-conductive layers deposited on a substrate'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–1991Patents assigned to SGS THOMSON MICROELECTRONICS (6)· patent assignee history
1989–1991Based in La Tronche, FR· patent location history
1990Based in Trets, FR· patent location history
1992–2005Patents assigned to NAT SEMICONDUCTOR CORP (124)· patent assignee history
1992–1998Based in Santa Clara, CA, US· patent location history
1992–1997Based in San Jose, CA, US· patent location history
1995–2017Based in Palo Alto, CA, US· patent location history
1998–2000Patents assigned to FOVEONICS INC (6)· patent assignee history
2002–2017Patents assigned to MAXIM INTEGRATED PRODUCTS (17)· patent assignee history
2009–2015Patents assigned to BERGEMONT ALBERT (9)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 124 | 1992–2005 |
| MAXIM INTEGRATED PRODUCTS | 17 | 2002–2017 |
| BERGEMONT ALBERTself | 9 | 2009–2015 |
| FOVEONICS INC | 6 | 1998–2000 |
| SGS THOMSON MICROELECTRONICS | 6 | 1989–1991 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 117 | 1995–2017 |
| Santa Clara, California, US | 18 | 1992–1998 |
| San Jose, California, US | 17 | 1992–1997 |
| La Tronche, FR | 6 | 1989–1991 |
| Trets, FR | 1 | 1990 |